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[PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodet
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From: |
Philippe Mathieu-Daudé |
|
Subject: |
[PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree |
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Date: |
Sat, 23 Oct 2021 23:47:42 +0200 |
Convert instructions with an immediate bit index and
data format df/m to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 15 +++++
target/mips/tcg/msa_translate.c | 98 ++++++++-------------------------
2 files changed, 39 insertions(+), 74 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5aaa85456da..91d71ff560c 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -22,6 +22,7 @@
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws=0
+@bit ...... ... df:7 ws:5 wd:5 ...... &msa_ldst sa=0
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
@@ -47,5 +48,19 @@ BNZ 010001 111 .. ..... ................
@bz
LDI 011110 110 .. .......... ..... 000111 @ldi
+ SLLI 011110 000 ....... ..... ..... 001001 @bit
+ SRAI 011110 001 ....... ..... ..... 001001 @bit
+ SRLI 011110 010 ....... ..... ..... 001001 @bit
+ BCLRI 011110 011 ....... ..... ..... 001001 @bit
+ BSETI 011110 100 ....... ..... ..... 001001 @bit
+ BNEGI 011110 101 ....... ..... ..... 001001 @bit
+ BINSLI 011110 110 ....... ..... ..... 001001 @bit
+ BINSRI 011110 111 ....... ..... ..... 001001 @bit
+
+ SAT_S 011110 000 ....... ..... ..... 001010 @bit
+ SAT_U 011110 001 ....... ..... ..... 001010 @bit
+ SRARI 011110 010 ....... ..... ..... 001010 @bit
+ SRLRI 011110 011 ....... ..... ..... 001010 @bit
+
MSA 011110 --------------------------
}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 962aef601cb..10bbe25172a 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
OPC_MSA_I8_00 = 0x00 | OPC_MSA,
OPC_MSA_I8_01 = 0x01 | OPC_MSA,
OPC_MSA_I8_02 = 0x02 | OPC_MSA,
- OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
- OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
OPC_MSA_3R_0D = 0x0D | OPC_MSA,
OPC_MSA_3R_0E = 0x0E | OPC_MSA,
OPC_MSA_3R_0F = 0x0F | OPC_MSA,
@@ -222,20 +220,6 @@ enum {
OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
-
- /* BIT instruction df(bits 22..16) = _B _H _W _D */
- OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
- OPC_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A,
- OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
- OPC_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A,
- OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
- OPC_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A,
- OPC_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09,
- OPC_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A,
- OPC_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09,
- OPC_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09,
- OPC_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
- OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
};
static const char msaregnames[][6] = {
@@ -547,78 +531,48 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
return true;
}
-static void gen_msa_bit(DisasContext *ctx)
+static bool trans_msa_bit(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_bit)(TCGv_ptr, TCGv_i32, TCGv_i32,
+ TCGv_i32, TCGv_i32))
{
-#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
TCGv_i32 tdf;
TCGv_i32 tm;
TCGv_i32 twd;
TCGv_i32 tws;
uint32_t df, m;
- if (!df_extract(df_bit, dfm, &df, &m)) {
+ if (!df_extract(df_bit, a->df, &df, &m)) {
gen_reserved_instruction(ctx);
- return;
+ return true;
}
- tdf = tcg_const_i32(df);
+ tdf = tcg_constant_i32(df);
tm = tcg_const_i32(m);
- twd = tcg_const_i32(wd);
- tws = tcg_const_i32(ws);
+ twd = tcg_const_i32(a->wd);
+ tws = tcg_const_i32(a->ws);
- switch (MASK_MSA_BIT(ctx->opcode)) {
- case OPC_SLLI_df:
- gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRAI_df:
- gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRLI_df:
- gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BCLRI_df:
- gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BSETI_df:
- gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BNEGI_df:
- gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BINSLI_df:
- gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_BINSRI_df:
- gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SAT_S_df:
- gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SAT_U_df:
- gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRARI_df:
- gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm);
- break;
- case OPC_SRLRI_df:
- gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
+ gen_msa_bit(cpu_env, tdf, twd, tws, tm);
- tcg_temp_free_i32(tdf);
tcg_temp_free_i32(tm);
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
+
+ return true;
}
+TRANS_MSA(SLLI, trans_msa_bit, gen_helper_msa_slli_df);
+TRANS_MSA(SRAI, trans_msa_bit, gen_helper_msa_srai_df);
+TRANS_MSA(SRLI, trans_msa_bit, gen_helper_msa_srli_df);
+TRANS_MSA(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df);
+TRANS_MSA(BSETI, trans_msa_bit, gen_helper_msa_bseti_df);
+TRANS_MSA(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df);
+TRANS_MSA(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df);
+TRANS_MSA(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df);
+TRANS_MSA(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df);
+TRANS_MSA(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df);
+TRANS_MSA(SRARI, trans_msa_bit, gen_helper_msa_srari_df);
+TRANS_MSA(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df);
+
static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -2151,10 +2105,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_I8_02:
gen_msa_i8(ctx);
break;
- case OPC_MSA_BIT_09:
- case OPC_MSA_BIT_0A:
- gen_msa_bit(ctx);
- break;
case OPC_MSA_3R_0D:
case OPC_MSA_3R_0E:
case OPC_MSA_3R_0F:
--
2.31.1
- [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, (continued)
- [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 10/33] target/mips: Extract df_extract() helper, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23