Re: [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)

[Richard Henderson]

On 10/24/21 10:37 AM, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> > +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
> > +                          enum CPUMIPSMSADataFormat df_base,
> > +                          void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
> > +                                              TCGv_i32, TCGv_i32))
> > +{
> > +    TCGv_i32 twd = tcg_const_i32(a->wd);
> > +    TCGv_i32 tws = tcg_const_i32(a->ws);
> > +    TCGv_i32 twt = tcg_const_i32(a->wt);
> > +    /* adjust df value for floating-point instruction */
> > +    TCGv_i32 tdf = tcg_constant_i32(a->df + df_base);
>
> I think it would be better to decode df completely in decodetree.
> E.g.
>
> %df_hw        21:1 !function=plus_1
> @3rf_hw       ...... .... . wt:5 ws:5 wd:5 ......  &msa_r df=%df_hw
>
> %df_wd        21:1 !function=plus_2
> @3rf_wd       ...... .... . wt:5 ws:5 wd:5 ......  &msa_r df=%df_wd

Meant to say, with that changed,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~