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[PATCH v2 29/32] target/mips: Convert CTCMSA opcode to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 29/32] target/mips: Convert CTCMSA opcode to decodetree |
Date: |
Wed, 27 Oct 2021 20:07:27 +0200 |
Convert the CTCMSA (Copy To Control MSA register) opcode
to decodetree. Since it overlaps with the SLDI opcode,
use a decodetree overlap group.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 5 ++-
target/mips/tcg/msa_translate.c | 69 ++++++---------------------------
2 files changed, 16 insertions(+), 58 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 12358e7a6ba..f3ec195bac0 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -165,7 +165,10 @@ BNZ 010001 111 .. ..... ................
@bz
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
- SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
+ {
+ CTCMSA 011110 0000111110 ..... ..... 011001 @elm
+ SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
+ }
{
CFCMSA 011110 0001111110 ..... ..... 011001 @elm
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 56db02f73e7..4a2a02bd6d2 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -25,18 +25,6 @@ static int msa_bit_df(DisasContext *ctx, int x);
/* Include the auto-generated decoder. */
#include "decode-msa.c.inc"
-#define OPC_MSA (0x1E << 26)
-
-#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
-enum {
- OPC_MSA_ELM = 0x19 | OPC_MSA,
-};
-
-enum {
- /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
- OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-};
-
static const char msaregnames[][6] = {
"w0.d0", "w0.d1", "w1.d0", "w1.d1",
"w2.d0", "w2.d1", "w3.d0", "w3.d1",
@@ -521,27 +509,22 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm
*a)
return true;
}
-static void gen_msa_elm_3e(DisasContext *ctx)
+static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
{
-#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
- uint8_t source = (ctx->opcode >> 11) & 0x1f;
- uint8_t dest = (ctx->opcode >> 6) & 0x1f;
- TCGv telm = tcg_temp_new();
- TCGv_i32 tdt = tcg_const_i32(dest);
+ TCGv telm;
- switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
- case OPC_CTCMSA:
- gen_load_gpr(telm, source);
- gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
+ if (!check_msa_enabled(ctx)) {
+ return true;
}
+ telm = tcg_temp_new();
+
+ gen_load_gpr(telm, a->ws);
+ gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd));
+
tcg_temp_free(telm);
- tcg_temp_free_i32(tdt);
+
+ return true;
}
static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
@@ -642,20 +625,6 @@ static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df
*a)
return trans_msa_elm_d64(ctx, a, gen_msa_insert);
}
-static void gen_msa_elm(DisasContext *ctx)
-{
- uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-
- if (dfn == 0x3E) {
- /* CTCMSA */
- gen_msa_elm_3e(ctx);
- return;
- } else {
- gen_reserved_instruction(ctx);
- return;
- }
-}
-
static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
enum CPUMIPSMSADataFormat df_base,
gen_helper_piiii *gen_msa_3rf)
@@ -798,21 +767,7 @@ TRANS_MSA(BSEL_V, trans_msa_vec, gen_helper_msa_bsel_v);
static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
{
- uint32_t opcode = ctx->opcode;
-
- if (!check_msa_enabled(ctx)) {
- return true;
- }
-
- switch (MASK_MSA_MINOR(opcode)) {
- case OPC_MSA_ELM:
- gen_msa_elm(ctx);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
+ gen_reserved_instruction(ctx);
return true;
}
--
2.31.1
- [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), (continued)
- [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 30/32] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 28/32] target/mips: Convert CFCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 29/32] target/mips: Convert CTCMSA opcode to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init(), Philippe Mathieu-Daudé, 2021/10/27
- Re: [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree, Philippe Mathieu-Daudé, 2021/10/27