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Re: [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax
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From: |
Alistair Francis |
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Subject: |
Re: [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax |
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Date: |
Thu, 28 Oct 2021 21:30:57 +1000 |
On Thu, Oct 28, 2021 at 6:22 PM Frank Chang <frank.chang@sifive.com> wrote:
>
> On Thu, Oct 28, 2021 at 12:45 PM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
>>
>> From: Chih-Min Chao <chihmin.chao@sifive.com>
>>
>> The sNaN propagation behavior has been changed since
>> cd20cee7 in https://github.com/riscv/riscv-isa-manual.
>>
>> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
>> Signed-off-by: Frank Chang <frank.chang@sifive.com>
>> Acked-by: Alistair Francis <alistair.francis@wdc.com>
>> Message-id: 20211016085428.3001501-3-frank.chang@sifive.com
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> target/riscv/fpu_helper.c | 16 ++++++++++++----
>> 1 file changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
>> index 8700516a14..d62f470900 100644
>> --- a/target/riscv/fpu_helper.c
>> +++ b/target/riscv/fpu_helper.c
>> @@ -174,14 +174,18 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t
>> rs1, uint64_t rs2)
>> {
>> float32 frs1 = check_nanbox_s(rs1);
>> float32 frs2 = check_nanbox_s(rs2);
>> - return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
>> + return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float32_minnum(frs1, frs2, &env->fp_status) :
>> + float32_minimum_number(frs1, frs2, &env->fp_status));
>> }
>>
>> uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
>> {
>> float32 frs1 = check_nanbox_s(rs1);
>> float32 frs2 = check_nanbox_s(rs2);
>> - return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status));
>> + return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float32_maxnum(frs1, frs2, &env->fp_status) :
>> + float32_maximum_number(frs1, frs2, &env->fp_status));
>> }
>>
>> uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
>> @@ -283,12 +287,16 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t
>> frs1, uint64_t frs2)
>>
>> uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
>> {
>> - return float64_minnum(frs1, frs2, &env->fp_status);
>> + return env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float64_minnum(frs1, frs2, &env->fp_status) :
>> + float64_minimum_number(frs1, frs2, &env->fp_status);
>> }
>>
>> uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
>> {
>> - return float64_maxnum(frs1, frs2, &env->fp_status);
>> + return env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float64_maxnum(frs1, frs2, &env->fp_status) :
>> + float64_maximum_number(frs1, frs2, &env->fp_status);
>> }
>>
>> uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
>> --
>> 2.31.1
>>
>
> Hi Alistair,
>
> Did you pull the latest v5 patchset?
> https://lists.nongnu.org/archive/html/qemu-riscv/2021-10/msg00557.html
Strange, I don't see it on the patches list. All I see is v4
Alistair
>
> I added more texts in the commit message to describe why we tie RVF version
> with Priv version.
> I think it's still okay to pull this one as I don't think there's any
> functional changes, IIRC.
>
> Regards,
> Frank Chang
- [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension, (continued)
- [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/28
- [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/28
- [PULL 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/28
- [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/28
- [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/28
- [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/28
- [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on, Alistair Francis, 2021/10/28
- [PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin, Alistair Francis, 2021/10/28
- [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax, Alistair Francis, 2021/10/28
[PULL 17/18] target/riscv: fix VS interrupts forwarding to HS, Alistair Francis, 2021/10/28
[PULL 18/18] target/riscv: remove force HS exception, Alistair Francis, 2021/10/28
Re: [PULL 00/18] riscv-to-apply queue, Richard Henderson, 2021/10/28