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[PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructi
From: |
frank . chang |
Subject: |
[PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions |
Date: |
Fri, 29 Oct 2021 16:58:47 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 0076ce5a0a9..48942129135 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1685,9 +1685,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
+GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.25.1
- [PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions, (continued)
- [PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/10/29
- [PATCH v9 37/76] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/10/29
- [PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/10/29
- [PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/10/29
- [PATCH v9 30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/10/29
- [PATCH v9 31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/10/29
- [PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/10/29
- [PATCH v9 40/76] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/10/29
- [PATCH v9 41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/10/29
- [PATCH v9 39/76] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/10/29
- [PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions,
frank . chang <=
- [PATCH v9 44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/10/29
- [PATCH v9 46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/10/29
- [PATCH v9 43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/10/29
- [PATCH v9 45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/10/29
- [PATCH v9 47/76] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/10/29
- [PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/10/29
- [PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/10/29
- [PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/10/29
- [PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/10/29
- [PATCH v9 51/76] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/10/29