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Re: [PATCH v2] target/mips: Fix Loongson-3A4000 MSAIR config register
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v2] target/mips: Fix Loongson-3A4000 MSAIR config register |
Date: |
Fri, 29 Oct 2021 20:01:14 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 |
On 10/26/21 20:09, Philippe Mathieu-Daudé wrote:
> When using the Loongson-3A4000 CPU, the MSAIR is returned with a
> zero value (because unimplemented). Checking on real hardware,
> this value appears incorrect:
>
> $ cat /proc/cpuinfo
> system type : generic-loongson-machine
> machine : loongson,generic
> cpu model : Loongson-3 V0.4 FPU V0.1
> model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
> isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1
> mips64r2
> ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext
> loongson-ext2
> ...
>
> Checking the CFCMSA opcode result with gdb we get 0x60140:
>
> Breakpoint 1, 0x00000001200037c4 in main ()
> 1: x/i $pc
> => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir
> (gdb) si
> 0x00000001200037c8 in main ()
> (gdb) i r v0
> v0: 0x60140
>
> MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12,
> so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000
> CPU model added in commit af868995e1b.
>
> Cc: Huacai Chen <chenhuacai@kernel.org>
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v2: Mask out bits 17/18
> ---
> target/mips/cpu-defs.c.inc | 1 +
> 1 file changed, 1 insertion(+)
Thanks, applied to mips-next.