Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructi

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Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructi

From:	Richard Henderson
Subject:	Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions
Date:	Sat, 30 Oct 2021 20:44:32 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/25/21 5:28 AM, Frédéric Pétrot wrote:

The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.

Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
---
  target/riscv/translate.c | 21 +++++++++++++++++++--
  1 file changed, 19 insertions(+), 2 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

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Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, (continued)
- [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Philippe Mathieu-Daudé, 2021/10/25
  - Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Richard Henderson, 2021/10/25
- [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Philippe Mathieu-Daudé, 2021/10/25
    - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Richard Henderson, 2021/10/25
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson, 2021/10/30
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Richard Henderson <=
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Philippe Mathieu-Daudé, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/25
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson, 2021/10/30
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Richard Henderson, 2021/10/30
- [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Richard Henderson, 2021/10/31
- [PATCH v4 14/17] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/25

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