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Re: [PATCH 06/13] target/riscv: Adjust vsetvl according to ol

From: Richard Henderson
Subject: Re: [PATCH 06/13] target/riscv: Adjust vsetvl according to ol
Date: Mon, 1 Nov 2021 06:53:09 -0400
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/1/21 6:01 AM, LIU Zhiwei wrote:
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
      } else {
          s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
-    gen_helper_vsetvl(dst, cpu_env, s1, s2);
+    gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_olen(ctx)));


+        if (olen < TARGET_LONG_BITS) {
+            env->vtype = FIELD_DP64(0, VTYPE, VILL_OLEN32, 1);
+        } else {
+            env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+        }

This looks like an excellent reason to split VILL out of VTYPE and create a separate env->vill field. Re-assemble it when reading the CSR, much like we do for misa.mxl. That would want to be a separate patch, of course.


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