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Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO

From: Peter Maydell
Subject: Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO
Date: Mon, 1 Nov 2021 18:03:07 +0000

On Tue, 26 Oct 2021 at 18:46, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Ah hah.  From 0487G.a, page D13-3191:
> # For other faults reported in ESR_EL2, ISV is 0 except
> # for the following stage 2 aborts...
> (which incidentally sounds like documenting around a historic chip bug, since 
> both EL1 and
> EL3 do get ISV set).

Nope, you have that the wrong way around: EL1 and EL3 get ISV=0 for
almost all cases -- only the FEAT_LS64 ST64BV/ST64BV0/ST64B/LD64B insns
cause a fault with ISV=1. For EL2, in addition to the FEAT_LS64 stuff,
you also get ISV=1 for the loads and stores which are emulatable
without having to load and decode the instruction word by hand,
because all the information you need to emulate them is in the ISS
fields. So you don't get ISV=1 for load/store pair because the ISS
doesn't have fields for more than one transfer register, and you
don't get ISV=1 for instructions doing register writeback because
that's not something the ISS gives you enough information to do, and so on.
And the reason that you only get this extra ISV=1 information for
these faults at EL2 is that the assumption is that only a hypervisor
needs to be doing this kind of emulate-and-continue of a data abort,
so the architecture absolves non-EL2 implementations of the need to
do all this work to track and report the information relating to the
insn that provoked the fault.

-- PMM

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