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[PULL 36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PULL 36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU |
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Date: |
Tue, 2 Nov 2021 14:42:35 +0100 |
FCR0_HAS2008 flag has been enabled in commit ba5c79f2622
("target-mips: indicate presence of IEEE 754-2008 FPU in
R6/R5+MSA CPUs"), so remove the obsolete FIXME comment.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028212103.2126176-1-f4bug@amsat.org>
---
target/mips/cpu-defs.c.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index ee8b322a564..582f9400702 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -369,7 +369,6 @@ const mips_def_t mips_defs[] =
* Config3: VZ, CTXTC, CDMM, TL
* Config4: MMUExtDef
* Config5: MRP
- * FIR(FCR0): Has2008
* */
.name = "P5600",
.CP0_PRid = 0x0001A800,
--
2.31.1
- [PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), (continued)
- [PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 27/41] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 28/41] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 29/41] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 30/41] target/mips: Convert MSA MOVE.V opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 31/41] target/mips: Convert CFCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 32/41] target/mips: Convert CTCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 33/41] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 34/41] target/mips: Remove one MSA unnecessary decodetree overlap group, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU,
Philippe Mathieu-Daudé <=
- [PULL 35/41] target/mips: Fix Loongson-3A4000 MSAIR config register, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 37/41] usb/uhci: Misc clean up, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 38/41] usb/uhci: Disallow user creating a vt82c686-uhci-pci device, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 39/41] usb/uhci: Replace pci_set_irq with qemu_set_irq, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 40/41] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 41/41] Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too", Philippe Mathieu-Daudé, 2021/11/02
- Re: [PULL 00/41] MIPS patches for 2021-11-02, Richard Henderson, 2021/11/02