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[PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc
From: |
David Gibson |
Subject: |
[PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc |
Date: |
Tue, 9 Nov 2021 16:51:38 +1100 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
There's no reason to keep vector-impl.c.inc separate from
vmx-impl.c.inc. Additionally, let GVec handle the multiple calls to
helper_cfuged for us.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-2-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 2 +-
target/ppc/int_helper.c | 2 +-
target/ppc/translate.c | 1 -
target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
target/ppc/translate/vector-impl.c.inc | 48 ----------------------
target/ppc/translate/vmx-impl.c.inc | 16 ++++++++
6 files changed, 19 insertions(+), 52 deletions(-)
delete mode 100644 target/ppc/translate/vector-impl.c.inc
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 72e66c5fe8..401575b935 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,7 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
-DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 913d76be6e..f03c864e48 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -324,7 +324,7 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
-uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+uint64_t helper_CFUGED(uint64_t src, uint64_t mask)
{
/*
* Instead of processing the mask bit-by-bit from the most significant to
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 659859ff5f..fc9d35a7a8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7407,7 +7407,6 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d,
arg_PLS_D *a)
#include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.c.inc"
-#include "translate/vector-impl.c.inc"
#include "translate/dfp-impl.c.inc"
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 220b099fcd..fa519c2d3e 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -407,7 +407,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
#if defined(TARGET_PPC64)
- gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+ gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
diff --git a/target/ppc/translate/vector-impl.c.inc
b/target/ppc/translate/vector-impl.c.inc
deleted file mode 100644
index 197e903337..0000000000
--- a/target/ppc/translate/vector-impl.c.inc
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Power ISA decode for Vector Facility instructions
- *
- * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
-{
- TCGv_i64 tgt, src, mask;
-
- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
- REQUIRE_VECTOR(ctx);
-
- tgt = tcg_temp_new_i64();
- src = tcg_temp_new_i64();
- mask = tcg_temp_new_i64();
-
- /* centrifuge lower double word */
- get_cpu_vsrl(src, a->vra + 32);
- get_cpu_vsrl(mask, a->vrb + 32);
- gen_helper_cfuged(tgt, src, mask);
- set_cpu_vsrl(a->vrt + 32, tgt);
-
- /* centrifuge higher double word */
- get_cpu_vsrh(src, a->vra + 32);
- get_cpu_vsrh(mask, a->vrb + 32);
- gen_helper_cfuged(tgt, src, mask);
- set_cpu_vsrh(a->vrt + 32, tgt);
-
- tcg_temp_free_i64(tgt);
- tcg_temp_free_i64(src);
- tcg_temp_free_i64(mask);
-
- return true;
-}
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 92b9527aff..e36c66589c 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1559,6 +1559,22 @@ GEN_VXFORM3(vpermxor, 22, 0xFF)
GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
+static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_CFUGED,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.33.1
- [PULL 15/54] host-utils: Introduce mulu128, (continued)
- [PULL 15/54] host-utils: Introduce mulu128, David Gibson, 2021/11/09
- [PULL 06/54] target/ppc: Implement PLQ and PSTQ, David Gibson, 2021/11/09
- [PULL 09/54] target/ppc: Implement pdepd instruction, David Gibson, 2021/11/09
- [PULL 13/54] target/ppc: Introduce REQUIRE_FPU, David Gibson, 2021/11/09
- [PULL 18/54] target/ppc: Do not update nip on DFP instructions, David Gibson, 2021/11/09
- [PULL 20/54] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree, David Gibson, 2021/11/09
- [PULL 16/54] libdecnumber: Introduce decNumberIntegralToInt128, David Gibson, 2021/11/09
- [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] to decodetree, David Gibson, 2021/11/09
- [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions, David Gibson, 2021/11/09
- [PULL 25/54] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree, David Gibson, 2021/11/09
- [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc,
David Gibson <=
- [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled, David Gibson, 2021/11/09
- [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions, David Gibson, 2021/11/09
- [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree, David Gibson, 2021/11/09
- [PULL 23/54] target/ppc: Move dqua[q], drrnd[q] to decodetree, David Gibson, 2021/11/09
- [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree, David Gibson, 2021/11/09
- [PULL 36/54] target/ppc: Implement Vector Extract Double to VSR using GPR index insns, David Gibson, 2021/11/09
- [PULL 32/54] target/ppc: Implement Vector Insert from GPR using GPR index insns, David Gibson, 2021/11/09
- [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents, David Gibson, 2021/11/09
- [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns, David Gibson, 2021/11/09
- [PULL 30/54] target/ppc: Implement vpdepd/vpextd instruction, David Gibson, 2021/11/09