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[PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch.
From: |
Xiaojuan Yang |
Subject: |
[PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch. |
Date: |
Tue, 9 Nov 2021 20:51:43 +0800 |
This patch introduces all possible exceptions.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 13 +++++++++++++
target/loongarch/cpu.h | 17 +++++++++++++++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index a53c8ebfb5..16443159cc 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -37,6 +37,19 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_BREAK] = "Break",
[EXCP_INE] = "Instruction Non-existent",
[EXCP_FPE] = "Floating Point Exception",
+ [EXCP_IPE] = "Error privilege level access",
+ [EXCP_TLBL] = "TLB load",
+ [EXCP_TLBS] = "TLB store",
+ [EXCP_INST_NOTAVAIL] = "TLB inst not exist",
+ [EXCP_TLBM] = "TLB modify",
+ [EXCP_TLBPE] = "TLB priviledged error",
+ [EXCP_TLBNX] = "TLB execute-inhibit",
+ [EXCP_TLBNR] = "TLB read-inhibit",
+ [EXCP_EXT_INTERRUPT] = "Interrupt",
+ [EXCP_DBP] = "Debug breakpoint",
+ [EXCP_IBE] = "Instruction bus error",
+ [EXCP_DBE] = "Data bus error",
+ [EXCP_DINT] = "Debug interrupt",
};
const char *loongarch_exception_name(int32_t exception)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 10fcd53104..399c4cb5e8 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -369,8 +369,21 @@ enum {
EXCP_BREAK,
EXCP_INE,
EXCP_FPE,
-
- EXCP_LAST = EXCP_FPE,
+ EXCP_IPE,
+ EXCP_TLBL,
+ EXCP_TLBS,
+ EXCP_INST_NOTAVAIL,
+ EXCP_TLBM,
+ EXCP_TLBPE,
+ EXCP_TLBNX,
+ EXCP_TLBNR,
+ EXCP_EXT_INTERRUPT,
+ EXCP_DBP,
+ EXCP_IBE,
+ EXCP_DBE,
+ EXCP_DINT,
+
+ EXCP_LAST = EXCP_DINT,
};
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
--
2.27.0
- [PATCH v2 00/30] Add Loongarch softmmu support., Xiaojuan Yang, 2021/11/09
- [PATCH v2 01/30] target/loongarch: Update README, Xiaojuan Yang, 2021/11/09
- [PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch.,
Xiaojuan Yang <=
- [PATCH v2 02/30] target/loongarch: Add CSR registers definition, Xiaojuan Yang, 2021/11/09
- [PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions(), Xiaojuan Yang, 2021/11/09
- [PATCH v2 12/30] target/loongarch: Add timer related instructions support., Xiaojuan Yang, 2021/11/09
- [PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU., Xiaojuan Yang, 2021/11/09