Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructi

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Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructi

From:	Richard Henderson
Subject:	Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions
Date:	Mon, 15 Nov 2021 09:30:31 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0

On 11/12/21 3:58 PM, Frédéric Pétrot wrote:

The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.

Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
---
  target/riscv/translate.c | 21 +++++++++++++++++++--
  1 file changed, 19 insertions(+), 2 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

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[PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, (continued)
- [PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/11/12
- [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/11/12
- [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/11/12
- [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/11/12
- [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson, 2021/11/15
    - Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/11/16
- [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Richard Henderson <=
  - Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Alistair Francis, 2021/11/24

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