[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and

From: Frédéric Pétrot
Subject: Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
Date: Tue, 16 Nov 2021 17:08:41 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.0

On 15/11/2021 09:29, Richard Henderson wrote:
On 11/12/21 3:58 PM, Frédéric Pétrot wrote:
+        tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? desth : destl, addrl,
+                           ctx->mem_idx, MO_TEUQ);

This isn't correct.  MO_BSWAP is related to the host, not the guest.

  Argh! Thx for pointing out my misunderstanding.
You want

     (memop & MO_BSWAP) == MO_LE ? destl : desth

Are there any big-endian RISC-V though?

  Not that I know of, but the spec defines it since V2.0 (bitfields MBE/SBE/UBE
  in mstatus), gcc supports it, and there is a check for it in get_dump_info
  for the riscv, so I opted for adding that (wrong) line.
  Since we can expect in the future endianness to be dynamic, you are probably
  right that we should assume litte-endian accesses for now, as handling both
  will anyway require many other changes.

| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA,   Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70      Ad augusta  per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |

reply via email to

[Prev in Thread] Current Thread [Next in Thread]