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Re: [PATCH v1 2/9] hw/arm/xlnx-versal: Connect Versal's PMC SLCR
From: |
Edgar E. Iglesias |
Subject: |
Re: [PATCH v1 2/9] hw/arm/xlnx-versal: Connect Versal's PMC SLCR |
Date: |
Fri, 19 Nov 2021 17:59:48 +0100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Wed, Nov 17, 2021 at 02:18:34PM +0000, Francisco Iglesias wrote:
> Connect Versal's PMC SLCR (system-level control registers) model.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
> ---
> hw/arm/xlnx-versal.c | 18 ++++++++++++++++++
> include/hw/arm/xlnx-versal.h | 6 ++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index b2705b6925..08e250945f 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -369,6 +369,23 @@ static void versal_create_efuse(Versal *s, qemu_irq *pic)
> sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
> }
>
> +static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic)
> +{
> + SysBusDevice *sbd;
> +
> + object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr",
> &s->pmc.iou.slcr,
> + TYPE_XILINX_VERSAL_PMC_IOU_SLCR);
> +
> + sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr);
> + sysbus_realize(sbd, &error_fatal);
> +
> + memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR,
> + sysbus_mmio_get_region(sbd, 0));
> +
> + sysbus_connect_irq(sbd, 0, pic[VERSAL_PMC_IOU_SLCR_IRQ]);
> +}
> +
> +
> /* This takes the board allocated linear DDR memory and creates aliases
> * for each split DDR range/aperture on the Versal address map.
> */
> @@ -459,6 +476,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
> versal_create_xrams(s, pic);
> versal_create_bbram(s, pic);
> versal_create_efuse(s, pic);
> + versal_create_pmc_iou_slcr(s, pic);
> versal_map_ddr(s);
> versal_unimp(s);
>
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index 895ba12c61..729c093dfc 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -26,6 +26,7 @@
> #include "hw/misc/xlnx-versal-xramc.h"
> #include "hw/nvram/xlnx-bbram.h"
> #include "hw/nvram/xlnx-versal-efuse.h"
> +#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
>
> #define TYPE_XLNX_VERSAL "xlnx-versal"
> OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
> @@ -78,6 +79,7 @@ struct Versal {
> struct {
> struct {
> SDHCIState sd[XLNX_VERSAL_NR_SDS];
> + XlnxVersalPmcIouSlcr slcr;
> } iou;
>
> XlnxZynqMPRTC rtc;
> @@ -113,6 +115,7 @@ struct Versal {
> #define VERSAL_XRAM_IRQ_0 79
> #define VERSAL_BBRAM_APB_IRQ_0 121
> #define VERSAL_RTC_APB_ERR_IRQ 121
> +#define VERSAL_PMC_IOU_SLCR_IRQ 121
> #define VERSAL_SD0_IRQ_0 126
> #define VERSAL_EFUSE_IRQ 139
> #define VERSAL_RTC_ALARM_IRQ 142
> @@ -178,6 +181,9 @@ struct Versal {
> #define MM_FPD_FPD_APU 0xfd5c0000
> #define MM_FPD_FPD_APU_SIZE 0x100
>
> +#define MM_PMC_PMC_IOU_SLCR 0xf1060000
> +#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
> +
> #define MM_PMC_SD0 0xf1040000U
> #define MM_PMC_SD0_SIZE 0x10000
> #define MM_PMC_BBRAM_CTRL 0xf11f0000
> --
> 2.11.0
>
- [PATCH v1 0/9] Xilinx Versal's PMC SLCR and OSPI support, Francisco Iglesias, 2021/11/17
- [PATCH v1 2/9] hw/arm/xlnx-versal: Connect Versal's PMC SLCR, Francisco Iglesias, 2021/11/17
- Re: [PATCH v1 2/9] hw/arm/xlnx-versal: Connect Versal's PMC SLCR,
Edgar E. Iglesias <=
- [PATCH v1 1/9] hw/misc: Add a model of Versal's PMC SLCR, Francisco Iglesias, 2021/11/17
- [PATCH v1 3/9] include/hw/dma/xlnx_csu_dma: Include ptimer.h and stream.h in the header, Francisco Iglesias, 2021/11/17
- [PATCH v1 4/9] hw/dma: Add the DMA control interface, Francisco Iglesias, 2021/11/17
- [PATCH v1 9/9] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI, Francisco Iglesias, 2021/11/17
- [PATCH v1 5/9] hw/dma/xlnx_csu_dma: Implement the DMA control interface, Francisco Iglesias, 2021/11/17