[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructio
From: |
Alistair Francis |
Subject: |
Re: [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions |
Date: |
Wed, 24 Nov 2021 16:21:21 +1000 |
On Sat, Nov 13, 2021 at 1:12 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> Adding the 128-bit version of lui and auipc, and introducing to that end
> a "set register with immediate" function to handle extension on 128 bits.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 21 +++++++++++++++++++++
> target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++----
> 2 files changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 508ae87985..d2a2f1021d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -289,6 +289,27 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num,
> TCGv t)
> }
> }
>
> +static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
> +{
> + if (reg_num != 0) {
> + switch (get_ol(ctx)) {
> + case MXL_RV32:
> + tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm);
> + break;
> + case MXL_RV64:
> + case MXL_RV128:
> + tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + if (get_xl_max(ctx) == MXL_RV128) {
> + tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0));
> + }
> + }
> +}
> +
> static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
> {
> assert(get_ol(ctx) == MXL_RV128);
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index fc73735b9e..0070fe606a 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -26,14 +26,14 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
>
> static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
> {
> - REQUIRE_64BIT(ctx);
> - return trans_illegal(ctx, a);
> + REQUIRE_64_OR_128BIT(ctx);
> + return trans_illegal(ctx, a);
> }
>
> static bool trans_lui(DisasContext *ctx, arg_lui *a)
> {
> if (a->rd != 0) {
> - tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
> + gen_set_gpri(ctx, a->rd, a->imm);
> }
> return true;
> }
> @@ -41,7 +41,7 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
> static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> {
> if (a->rd != 0) {
> - tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
> + gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> }
> return true;
> }
> --
> 2.33.1
>
>
- [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, (continued)
- [PATCH v5 02/18] exec/memop: Adding signed quad and octo defines, Frédéric Pétrot, 2021/11/12
- [PATCH v5 04/18] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/11/12
- [PATCH v5 07/18] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/11/12
- [PATCH v5 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/11/12
- Re: [PATCH v5 11/18] target/riscv: support for 128-bit U-type instructions,
Alistair Francis <=
- [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 2021/11/12
- [PATCH v5 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/11/12
- [PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/11/12
- [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/11/12
- [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/11/12
- [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/11/12