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Re: [for-6.2] hw/intc/arm_gicv3: Update cached state after acknowledging

From: Peter Maydell
Subject: Re: [for-6.2] hw/intc/arm_gicv3: Update cached state after acknowledging LPI
Date: Wed, 24 Nov 2021 17:09:58 +0000

On Tue, 23 Nov 2021 at 19:22, Shashi Mallela <shashi.mallela@linaro.org> wrote:
> Since LPIs do not have an active or active and pending state,the current 
> implementation only clears the LPI pending state from the pending table once 
> ICC_IAR1_EL1 acknowledges the interrupt.
> But, as part of gicv3_lpi_pending() processing, cs->hpplpi is updated with 
> the next best priotiy lpi (only if the current acknowledged irq was best 
> priority irq).

Yes. But we don't update cs->hppi there, and the GIC code assumes
that that cs->hppi always indicates the highest priority pending
interrupt, so leaving it stale will break things.

> By calling gicv3_redist_update() in icc_activate_irq(), we are
> re-initiating high priority irqs scan in redistributor and if
> applicable trigger of next best pending lpi from the latest
> cs->hpplpi info (which otherwise would have happened on next
> irq trigger from source).

We will figure out which the next best pending interrupt is
(which might be an LPI or might be some other interrupt).
But we won't actually trigger it, because it must be lower
priority than the LPI that we are activating.

(The way this works is that activating the LPI in icc_activate_irq()
writes into the Active Priority Registers to indicate the priority
of the current active interrupt. When gicv3_cpuif_update() is
deciding whether to set IRQ/FIQ to tell the CPU it has an interrupt
it calls icc_hppi_can_preempt(), which checks the priority of the
pending interrupt recorded in cs->hppi against the priority
of the active interrupt as calculated by icc_highest_active_prio().
So we won't take another interrupt until either (a) this one is
deactivated or (b) a fresh one arrives at a higher priority.)

-- PMM

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