Re: [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl

qemu-devel

From:	Richard Henderson
Subject:	Re: [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl
Date:	Fri, 26 Nov 2021 12:19:54 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0

On 11/25/21 8:39 AM, LIU Zhiwei wrote:

+static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
+{
+    if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {

Let's make this != MXL_RV32. I suppose real RV128 will extend this restriction to mod 4,but that is not yet documented.


Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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[PATCH v5 00/22] Support UXL filed in xstatus, LIU Zhiwei, 2021/11/25
- [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 2021/11/25
  - Re: [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl, Richard Henderson <=
- [PATCH v5 02/22] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/25
- [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 04/22] target/riscv: Create xl field in env, LIU Zhiwei, 2021/11/25
  - Re: [PATCH v5 04/22] target/riscv: Create xl field in env, Richard Henderson, 2021/11/26
- [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/25
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/25
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/25
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 10/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/25