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[PATCH v10 10/77] target/riscv: rvv-1.0: add vlenb register
From: |
frank . chang |
Subject: |
[PATCH v10 10/77] target/riscv: rvv-1.0: add vlenb register |
Date: |
Mon, 29 Nov 2021 11:02:30 +0800 |
From: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8dc6aa62c64..1e31f4d35f5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -63,6 +63,7 @@
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 832ccdcf331..5d1eec1ea05 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -285,6 +285,12 @@ static RISCVException read_vl(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env_archcpu(env)->cfg.vlen >> 3;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_vxrm(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1835,6 +1841,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
+ [CSR_VLENB] = { "vlenb", vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { "cycle", ctr, read_instret },
[CSR_INSTRET] = { "instret", ctr, read_instret },
--
2.25.1
- [PATCH v10 00/77] support vector extension v1.0, frank . chang, 2021/11/28
- [PATCH v10 03/77] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/11/28
- [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, frank . chang, 2021/11/28
- [PATCH v10 05/77] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/11/28
- [PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/11/28
- [PATCH v10 07/77] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/11/28
- [PATCH v10 10/77] target/riscv: rvv-1.0: add vlenb register,
frank . chang <=
- [PATCH v10 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/11/28
- [PATCH v10 09/77] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/11/28
- [PATCH v10 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/11/28
- [PATCH v10 14/77] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/11/28
- [PATCH v10 16/77] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/11/28
- [PATCH v10 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2021/11/28
- [PATCH v10 18/77] target/riscv: rvv-1.0: remove amo operations instructions, frank . chang, 2021/11/28
- [PATCH v10 19/77] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/11/28
- [PATCH v10 20/77] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/11/28
- [PATCH v10 21/77] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2021/11/28