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[PATCH v10 37/77] target/riscv: rvv-1.0: floating-point move instruction
From: |
frank . chang |
Subject: |
[PATCH v10 37/77] target/riscv: rvv-1.0: floating-point move instruction |
Date: |
Mon, 29 Nov 2021 11:02:57 +0800 |
From: Frank Chang <frank.chang@sifive.com>
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index c250943dde8..2c8002af543 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2461,9 +2461,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
+ TCGv_i64 t1;
+
if (s->vl_eq_vlmax) {
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ MAXSZ(s), MAXSZ(s), t1);
mark_vs_dirty(s);
} else {
TCGv_ptr dest;
@@ -2477,15 +2483,21 @@ static bool trans_vfmv_v_f(DisasContext *s,
arg_vfmv_v_f *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
dest = tcg_temp_new_ptr();
desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ fns[s->sew - 1](dest, t1, cpu_env, desc);
tcg_temp_free_ptr(dest);
mark_vs_dirty(s);
gen_set_label(over);
}
+ tcg_temp_free_i64(t1);
return true;
}
return false;
--
2.25.1
- [PATCH v10 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, (continued)
- [PATCH v10 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/11/28
- [PATCH v10 27/77] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/11/28
- [PATCH v10 28/77] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/11/28
- [PATCH v10 29/77] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 2021/11/28
- [PATCH v10 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/11/28
- [PATCH v10 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/11/28
- [PATCH v10 32/77] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/11/28
- [PATCH v10 33/77] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/11/28
- [PATCH v10 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/11/28
- [PATCH v10 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/11/28
- [PATCH v10 37/77] target/riscv: rvv-1.0: floating-point move instruction,
frank . chang <=
- [PATCH v10 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/11/28
- [PATCH v10 39/77] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/11/28
- [PATCH v10 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/11/28
- [PATCH v10 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/11/28
- [PATCH v10 42/77] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/11/28
- [PATCH v10 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/11/28
- [PATCH v10 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/11/28
- [PATCH v10 47/77] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/11/28
- [PATCH v10 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/11/28
- [PATCH v10 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/11/28