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[PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_
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From: |
frank . chang |
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Subject: |
[PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() |
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Date: |
Mon, 29 Nov 2021 11:03:33 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 946dca53ffd..83373ca6fc6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -279,15 +279,15 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
/* unmasked unit-stride load and store operation*/
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
- vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uintptr_t ra, MMUAccessType access_type)
+ vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl,
+ uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, esz);
/* load bytes from guest memory */
- for (i = env->vstart; i < env->vl; i++, env->vstart++) {
+ for (i = env->vstart; i < evl; i++, env->vstart++) {
k = 0;
while (k < nf) {
target_ulong addr = base + ((i * nf + k) << esz);
@@ -316,7 +316,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base,
\
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, LOAD_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \
}
GEN_VEXT_LD_US(vle8_v, int8_t, lde_b)
@@ -324,20 +324,20 @@ GEN_VEXT_LD_US(vle16_v, int16_t, lde_h)
GEN_VEXT_LD_US(vle32_v, int32_t, lde_w)
GEN_VEXT_LD_US(vle64_v, int64_t, lde_d)
-#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
-void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
- vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
-} \
- \
-void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- vext_ldst_us(vd, base, env, desc, STORE_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
+#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
+void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
+ vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
+} \
+ \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_us(vd, base, env, desc, STORE_FN, \
+ ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \
}
GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
--
2.25.1
- [PATCH v10 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, (continued)
- [PATCH v10 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/11/28
- [PATCH v10 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/11/28
- [PATCH v10 66/77] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/11/28
- [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/11/28
- [PATCH v10 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/11/28
- [PATCH v10 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/11/28
- [PATCH v10 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/11/28
- [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/11/28
- [PATCH v10 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/11/28
- [PATCH v10 72/77] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/11/28
- [PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(),
frank . chang <=
- [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/11/28
- [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/11/28
- [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/11/28
- [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/11/28
- [PATCH v10 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/11/28
- [PATCH v10 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/11/28
- [PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/11/28
- [PATCH v10 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/11/28
- [PATCH v10 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/11/28
- [PATCH v10 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/11/28