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[PATCH v10 46/77] target/riscv: rvv-1.0: single-width saturating add and
From: |
frank . chang |
Subject: |
[PATCH v10 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions |
Date: |
Mon, 29 Nov 2021 11:03:06 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index f6202835ff4..ed4554b6a1d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1999,7 +1999,7 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check)
GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
--
2.25.1
- [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, (continued)
- [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/11/28
- [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/11/28
- [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/11/28
- [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/11/28
- [PATCH v10 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/11/28
- [PATCH v10 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/11/28
- [PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/11/28
- [PATCH v10 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/11/28
- [PATCH v10 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/11/28
- [PATCH v10 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/11/28
- [PATCH v10 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions,
frank . chang <=