Hi; this is a collection of mostly GIC related patches for rc3.
The "Update cached state after LPI state changes" fix is important
and fixes what would otherwise be a regression since we enable the
ITS by default in the virt board now. The others are not regressions
but I think are OK for rc3 as they're fairly self contained (and two
of them are fixes to new-in-6.2 functionality).
thanks
-- PMM
The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a:
Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20211129
for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9:
hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29
10:10:21 +0000)
----------------------------------------------------------------
target-arm queue:
* virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
* GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
* GICv3: Update cached state after LPI state changes
* GICv3: Fix handling of LPIs in list registers
----------------------------------------------------------------
Alexander Graf (1):
hw/arm/virt: Extend nested and mte checks to hvf
Peter Maydell (3):
hw/intc/arm_gicv3: Update cached state after LPI state changes
hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
hw/intc/arm_gicv3: fix handling of LPIs in list registers
Shashi Mallela (1):
hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
hw/intc/gicv3_internal.h | 30 ++++++++++++++++++++++++++++++
hw/arm/virt.c | 15 +++++++++------
hw/intc/arm_gicv3.c | 6 ++++--
hw/intc/arm_gicv3_cpuif.c | 9 ++++-----
hw/intc/arm_gicv3_its.c | 7 ++++---
hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
6 files changed, 61 insertions(+), 20 deletions(-)