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[PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
From: |
frank . chang |
Subject: |
[PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 |
Date: |
Fri, 10 Dec 2021 15:56:57 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 952768f8de..d7c6bc9af2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -78,7 +78,7 @@
@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
-@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -671,7 +671,7 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111
@r2_vm
vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
-vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
+vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32 Zba Standard Extension ***
--
2.31.1
- [PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum, (continued)
- [PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/12/10
- [PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/12/10
- [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/12/10
- [PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/12/10
- [PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/12/10
- [PATCH v11 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/12/10
- [PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/12/10
- [PATCH v11 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/12/10
- [PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11,
frank . chang <=
- [PATCH v11 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/12/10
- [PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/12/10
- [PATCH v11 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/12/10
- [PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/12/10
- [PATCH v11 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/12/10
- [PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/12/10
- [PATCH v11 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/12/10
- Re: [PATCH v11 00/77] support vector extension v1.0, Alistair Francis, 2021/12/16