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[PATCH v7 15/18] target/riscv: adding high part of some csrs
From: |
Frédéric Pétrot |
Subject: |
[PATCH v7 15/18] target/riscv: adding high part of some csrs |
Date: |
Mon, 13 Dec 2021 17:38:31 +0100 |
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 603ae04837..a7c2e5c93e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -193,6 +193,10 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
+ /* Upper 64-bits of 128-bit CSRs */
+ uint64_t mscratchh;
+ uint64_t sscratchh;
+
/* Virtual CSRs */
/*
* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 8af9caabf5..13b9ab375b 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -179,6 +179,8 @@ static const VMStateDescription vmstate_rv128 = {
.needed = rv128_needed,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
+ VMSTATE_UINT64(env.mscratchh, RISCVCPU),
+ VMSTATE_UINT64(env.sscratchh, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
--
2.34.1
- [PATCH v7 11/18] target/riscv: support for 128-bit U-type instructions, (continued)
- [PATCH v7 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 2021/12/13
- [PATCH v7 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/12/13
- [PATCH v7 07/18] target/riscv: setup everything for rv64 to support rv128 execution, Frédéric Pétrot, 2021/12/13
- [PATCH v7 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/12/13
- [PATCH v7 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/12/13
- [PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/12/13
- [PATCH v7 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/12/13
- [PATCH v7 15/18] target/riscv: adding high part of some csrs,
Frédéric Pétrot <=
- [PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/12/13