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[PATCH v9 27/31] tcg/loongarch64: Register the JIT
From: |
WANG Xuerui |
Subject: |
[PATCH v9 27/31] tcg/loongarch64: Register the JIT |
Date: |
Tue, 14 Dec 2021 16:01:50 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 44 ++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index ff167d686b..8ce30ecae5 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1631,3 +1631,47 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_LOONGARCH
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+ .h.cie.return_column = TCG_REG_RA,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */
+ 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */
+ 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */
+ 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */
+ 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */
+ 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */
+ 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */
+ 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */
+ 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */
+ 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */
+ 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
+ }
+};
+
+void tcg_register_jit(const void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
--
2.34.0
- [PATCH v9 19/31] tcg/loongarch64: Implement br/brcond ops, (continued)
- [PATCH v9 19/31] tcg/loongarch64: Implement br/brcond ops, WANG Xuerui, 2021/12/14
- [PATCH v9 21/31] tcg/loongarch64: Implement tcg_out_call, WANG Xuerui, 2021/12/14
- [PATCH v9 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops, WANG Xuerui, 2021/12/14
- [PATCH v9 20/31] tcg/loongarch64: Implement setcond ops, WANG Xuerui, 2021/12/14
- [PATCH v9 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue, WANG Xuerui, 2021/12/14
- [PATCH v9 25/31] tcg/loongarch64: Implement exit_tb/goto_tb, WANG Xuerui, 2021/12/14
- [PATCH v9 31/31] tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab, WANG Xuerui, 2021/12/14
- [PATCH v9 22/31] tcg/loongarch64: Implement simple load/store ops, WANG Xuerui, 2021/12/14
- [PATCH v9 26/31] tcg/loongarch64: Implement tcg_target_init, WANG Xuerui, 2021/12/14
- [PATCH v9 27/31] tcg/loongarch64: Register the JIT,
WANG Xuerui <=
- [PATCH v9 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops, WANG Xuerui, 2021/12/14
- [PATCH v9 30/31] configure, meson.build: Mark support for loongarch64 hosts, WANG Xuerui, 2021/12/14
- [PATCH v9 29/31] linux-user: Implement CPU-specific signal handler for loongarch64 hosts, WANG Xuerui, 2021/12/14
- [PATCH v9 28/31] common-user: Add safe syscall handling for loongarch64 hosts, WANG Xuerui, 2021/12/14
- Re: [PATCH v9 28/31] common-user: Add safe syscall handling for loongarch64 hosts, Richard Henderson, 2021/12/14