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[PULL 032/101] target/ppc: Fix VXCVI return value
From: |
Cédric Le Goater |
Subject: |
[PULL 032/101] target/ppc: Fix VXCVI return value |
Date: |
Thu, 16 Dec 2021 21:25:05 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-14-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index be460cc74451..d471a0a1b89b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -585,13 +585,20 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1,
float64 arg2)
return ret;
}
-static void float_invalid_cvt(CPUPPCState *env, int flags,
- bool set_fprc, uintptr_t retaddr)
-{
- float_invalid_op_vxcvi(env, set_fprc, retaddr);
+static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
+ uint64_t ret, uint64_t ret_nan,
+ bool set_fprc, uintptr_t retaddr)
+{
+ /*
+ * VXCVI is different from most in that it sets two exception bits,
+ * VXCVI and VXSNAN for an SNaN input.
+ */
if (flags & float_flag_invalid_snan) {
- float_invalid_op_vxsnan(env, retaddr);
+ env->fpscr |= FP_VXSNAN;
}
+ float_invalid_op_vxcvi(env, set_fprc, retaddr);
+
+ return flags & float_flag_invalid_cvti ? ret : ret_nan;
}
#define FPU_FCTI(op, cvt, nanval) \
@@ -599,10 +606,8 @@ uint64_t helper_##op(CPUPPCState *env, float64 arg)
\
{ \
uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
int flags = get_float_exception_flags(&env->fp_status); \
- \
if (unlikely(flags & float_flag_invalid)) { \
- float_invalid_cvt(env, flags, 1, GETPC()); \
- ret = nanval; \
+ ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \
} \
return ret; \
}
@@ -2794,8 +2799,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb) \
t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
flags = env->fp_status.float_exception_flags; \
if (unlikely(flags & float_flag_invalid)) { \
- float_invalid_cvt(env, flags, 0, GETPC()); \
- t.tfld = rnan; \
+ t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
} \
all_flags |= flags; \
} \
@@ -2842,8 +2846,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode,
\
t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
flags = get_float_exception_flags(&env->fp_status); \
if (flags & float_flag_invalid) { \
- float_invalid_cvt(env, flags, 0, GETPC()); \
- t.tfld = rnan; \
+ t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \
} \
\
*xt = t; \
--
2.31.1
- [PULL 061/101] ppc/ppc405: Change kernel load address, (continued)
- [PULL 061/101] ppc/ppc405: Change kernel load address, Cédric Le Goater, 2021/12/16
- [PULL 053/101] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp, Cédric Le Goater, 2021/12/16
- [PULL 068/101] ppc/ppc405: Remove flash support, Cédric Le Goater, 2021/12/16
- [PULL 077/101] target/ppc: fix xscvqpdp register access, Cédric Le Goater, 2021/12/16
- [PULL 038/101] target/ppc: Split out do_fmadd, Cédric Le Goater, 2021/12/16
- [PULL 040/101] target/ppc: Split out do_frsp, Cédric Le Goater, 2021/12/16
- [PULL 041/101] target/ppc: Update do_frsp for new flags, Cédric Le Goater, 2021/12/16
- [PULL 044/101] target/ppc: Update xsrqpi and xsrqpxp to new flags, Cédric Le Goater, 2021/12/16
- [PULL 045/101] target/ppc: Update fre to new flags, Cédric Le Goater, 2021/12/16
- [PULL 022/101] softfloat: Add flag specific to Inf * 0, Cédric Le Goater, 2021/12/16
- [PULL 032/101] target/ppc: Fix VXCVI return value,
Cédric Le Goater <=
- [PULL 043/101] target/ppc: Update sqrt for new flags, Cédric Le Goater, 2021/12/16
- [PULL 050/101] target/ppc: Add helper for fmuls, Cédric Le Goater, 2021/12/16
- [PULL 047/101] target/ppc: Add helpers for fmadds et al, Cédric Le Goater, 2021/12/16
- [PULL 054/101] target/ppc: Disable software TLB for the 7450 family, Cédric Le Goater, 2021/12/16
- [PULL 060/101] target/ppc: remove 401/403 CPUs, Cédric Le Goater, 2021/12/16
- [PULL 062/101] ppc: Mark the 'taihu' machine as deprecated, Cédric Le Goater, 2021/12/16
- [PULL 064/101] ppc/ppc405: Convert printfs to trace-events, Cédric Le Goater, 2021/12/16
- [PULL 058/101] target/ppc: Remove 603e exception model, Cédric Le Goater, 2021/12/16
- [PULL 080/101] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp", Cédric Le Goater, 2021/12/16
- [PULL 070/101] ppc/ppc405: Introduce ppc405_set_default_bootinfo(), Cédric Le Goater, 2021/12/16