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[PULL 067/101] ppc/ppc405: Add some address space definitions
From: |
Cédric Le Goater |
Subject: |
[PULL 067/101] ppc/ppc405: Add some address space definitions |
Date: |
Thu, 16 Dec 2021 21:25:40 +0100 |
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 7 +++++++
hw/ppc/ppc405_boards.c | 16 +++++++---------
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ad5f4026b5db..ea48c3626908 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -27,6 +27,13 @@
#include "hw/ppc/ppc4xx.h"
+#define PPC405EP_SDRAM_BASE 0x00000000
+#define PPC405EP_NVRAM_BASE 0xF0000000
+#define PPC405EP_FPGA_BASE 0xF0300000
+#define PPC405EP_SRAM_BASE 0xFFF00000
+#define PPC405EP_SRAM_SIZE (512 * KiB)
+#define PPC405EP_FLASH_BASE 0xFFF80000
+
/* Bootinfo as set-up by u-boot */
typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
struct ppc4xx_bd_info_t {
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index fcdb6d4cf8a0..60dc81fa4880 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -154,7 +154,6 @@ static void ref405ep_init(MachineState *machine)
ram_addr_t bdloc;
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
- target_ulong sram_size;
long bios_size;
//int phy_addr = 0;
//static int phy_addr = 1;
@@ -187,10 +186,9 @@ static void ref405ep_init(MachineState *machine)
env = &cpu->env;
/* allocate SRAM */
- sram_size = 512 * KiB;
- memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
+ memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
&error_fatal);
- memory_region_add_subregion(sysmem, 0xFFF00000, sram);
+ memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
/* allocate and load BIOS */
#ifdef USE_FLASH_BIOS
dinfo = drive_get(IF_PFLASH, 0, 0);
@@ -230,24 +228,24 @@ static void ref405ep_init(MachineState *machine)
}
}
/* Register FPGA */
- ref405ep_fpga_init(sysmem, 0xF0300000);
+ ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
/* Register NVRAM */
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, 0xF0000000);
+ sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
/* Load kernel */
linux_boot = (kernel_filename != NULL);
if (linux_boot) {
memset(&bd, 0, sizeof(bd));
- bd.bi_memstart = 0x00000000;
+ bd.bi_memstart = PPC405EP_SDRAM_BASE;
bd.bi_memsize = machine->ram_size;
bd.bi_flashstart = -bios_size;
bd.bi_flashsize = -bios_size;
bd.bi_flashoffset = 0;
- bd.bi_sramstart = 0xFFF00000;
- bd.bi_sramsize = sram_size;
+ bd.bi_sramstart = PPC405EP_SRAM_BASE;
+ bd.bi_sramsize = PPC405EP_SRAM_SIZE;
bd.bi_bootflags = 0;
bd.bi_intfreq = 133333333;
bd.bi_busfreq = 33333333;
--
2.31.1
- [PULL 076/101] target/ppc: Move xs{max,min}[cj]dp to decodetree, (continued)
- [PULL 076/101] target/ppc: Move xs{max,min}[cj]dp to decodetree, Cédric Le Goater, 2021/12/16
- [PULL 092/101] ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize(), Cédric Le Goater, 2021/12/16
- [PULL 087/101] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Cédric Le Goater, 2021/12/16
- [PULL 083/101] target/ppc: PMU: update counters on PMCs r/w, Cédric Le Goater, 2021/12/16
- [PULL 091/101] ppc/pnv: Drop the "num-phbs" property, Cédric Le Goater, 2021/12/16
- [PULL 096/101] ppc/pnv: Introduce a "chip" property under the PHB4 model, Cédric Le Goater, 2021/12/16
- [PULL 082/101] target/ppc: PMU basic cycle count for pseries TCG, Cédric Le Goater, 2021/12/16
- [PULL 074/101] ppc/ppc405: Add update of bi_procfreq field, Cédric Le Goater, 2021/12/16
- [PULL 072/101] ppc/ppc405: Change default PLL values at reset, Cédric Le Goater, 2021/12/16
- [PULL 066/101] ppc/ppc405: Change ppc405ep_init() return value, Cédric Le Goater, 2021/12/16
- [PULL 067/101] ppc/ppc405: Add some address space definitions,
Cédric Le Goater <=
- [PULL 088/101] PPC64/TCG: Implement 'rfebb' instruction, Cédric Le Goater, 2021/12/16
- [PULL 085/101] target/ppc: enable PMU counter overflow with cycle events, Cédric Le Goater, 2021/12/16
- [PULL 057/101] target/ppc: Fix MPCxxx FPU interrupt address, Cédric Le Goater, 2021/12/16
- [PULL 086/101] target/ppc: enable PMU instruction count, Cédric Le Goater, 2021/12/16
- [PULL 097/101] ppc/pnv: Introduce a num_stack class attribute, Cédric Le Goater, 2021/12/16
- [PULL 098/101] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/16
- [PULL 100/101] ppc/pnv: Move realize of PEC stacks under the PEC model, Cédric Le Goater, 2021/12/16
- [PULL 099/101] ppc/pnv: Remove "system-memory" property from PHB4 PEC, Cédric Le Goater, 2021/12/16
- [PULL 095/101] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices, Cédric Le Goater, 2021/12/16
- [PULL 093/101] ppc/pnv: Use QOM hierarchy to scan PHB3 devices, Cédric Le Goater, 2021/12/16