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[PATCH 06/20] tcg/i386: Add tcg_out_evex_opc
From: |
Richard Henderson |
Subject: |
[PATCH 06/20] tcg/i386: Add tcg_out_evex_opc |
Date: |
Sat, 18 Dec 2021 11:42:36 -0800 |
The evex encoding is added here, for use in a subsequent patch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 51 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index e266f937d6..44d2919047 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -261,6 +261,7 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */
#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */
#define P_VEXL 0x80000 /* Set VEX.L = 1 */
+#define P_EVEX 0x100000 /* Requires EVEX encoding */
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
@@ -623,9 +624,57 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r,
int v,
tcg_out8(s, opc);
}
+static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v,
+ int rm, int index)
+{
+ /* The entire 4-byte evex prefix; with R' and V' set. */
+ uint32_t p = 0x08041062;
+ int mm, pp;
+
+ tcg_debug_assert(have_avx512vl);
+
+ /* EVEX.mm */
+ if (opc & P_EXT3A) {
+ mm = 3;
+ } else if (opc & P_EXT38) {
+ mm = 2;
+ } else if (opc & P_EXT) {
+ mm = 1;
+ } else {
+ g_assert_not_reached();
+ }
+
+ /* EVEX.pp */
+ if (opc & P_DATA16) {
+ pp = 1; /* 0x66 */
+ } else if (opc & P_SIMDF3) {
+ pp = 2; /* 0xf3 */
+ } else if (opc & P_SIMDF2) {
+ pp = 3; /* 0xf2 */
+ } else {
+ pp = 0;
+ }
+
+ p = deposit32(p, 8, 2, mm);
+ p = deposit32(p, 13, 1, (rm & 8) == 0); /* EVEX.RXB.B */
+ p = deposit32(p, 14, 1, (index & 8) == 0); /* EVEX.RXB.X */
+ p = deposit32(p, 15, 1, (r & 8) == 0); /* EVEX.RXB.R */
+ p = deposit32(p, 16, 2, pp);
+ p = deposit32(p, 19, 4, ~v);
+ p = deposit32(p, 23, 1, (opc & P_VEXW) != 0);
+ p = deposit32(p, 29, 2, (opc & P_VEXL) != 0);
+
+ tcg_out32(s, p);
+ tcg_out8(s, opc);
+}
+
static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
{
- tcg_out_vex_opc(s, opc, r, v, rm, 0);
+ if (opc & P_EVEX) {
+ tcg_out_evex_opc(s, opc, r, v, rm, 0);
+ } else {
+ tcg_out_vex_opc(s, opc, r, v, rm, 0);
+ }
tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
--
2.25.1
- [PATCH 00/20] tcg: vector improvements, Richard Henderson, 2021/12/18
- [PATCH 01/20] tcg/optimize: Fix folding of vector ops, Richard Henderson, 2021/12/18
- [PATCH 04/20] tcg/s390x: Implement vector NAND, NOR, EQV, Richard Henderson, 2021/12/18
- [PATCH 02/20] tcg: Add opcodes for vector nand, nor, eqv, Richard Henderson, 2021/12/18
- [PATCH 03/20] tcg/ppc: Implement vector NAND, NOR, EQV, Richard Henderson, 2021/12/18
- [PATCH 05/20] tcg/i386: Detect AVX512, Richard Henderson, 2021/12/18
- [PATCH 06/20] tcg/i386: Add tcg_out_evex_opc,
Richard Henderson <=
- [PATCH 07/20] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv, Richard Henderson, 2021/12/18
- [PATCH 08/20] tcg/i386: Implement avx512 variable shifts, Richard Henderson, 2021/12/18
- [PATCH 09/20] tcg/i386: Implement avx512 scalar shift, Richard Henderson, 2021/12/18
- [PATCH 11/20] tcg/i386: Implement avx512 immediate rotate, Richard Henderson, 2021/12/18
- [PATCH 13/20] tcg/i386: Support avx512vbmi2 vector shift-double instructions, Richard Henderson, 2021/12/18
- [PATCH 10/20] tcg/i386: Implement avx512 immediate sari shift, Richard Henderson, 2021/12/18
- [PATCH 12/20] tcg/i386: Implement avx512 variable rotate, Richard Henderson, 2021/12/18
- [PATCH 15/20] tcg/i386: Remove rotls_vec from tcg_target_op_def, Richard Henderson, 2021/12/18
- [PATCH 14/20] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double, Richard Henderson, 2021/12/18
- [PATCH 19/20] tcg/i386: Implement more logical operations for avx512, Richard Henderson, 2021/12/18