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[PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instru
From: |
Alistair Francis |
Subject: |
[PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions |
Date: |
Mon, 20 Dec 2021 14:56:30 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-46-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a3f1101cd6..7548b71efd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -474,9 +474,9 @@ vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm
-vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
+vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
--
2.31.1
- [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions, (continued)
- [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions, Alistair Francis, 2021/12/20
- [PULL 40/88] target/riscv: rvv-1.0: iota instruction, Alistair Francis, 2021/12/20
- [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended, Alistair Francis, 2021/12/20
- [PULL 41/88] target/riscv: rvv-1.0: element index instruction, Alistair Francis, 2021/12/20
- [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction, Alistair Francis, 2021/12/20
- [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions, Alistair Francis, 2021/12/20
- [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions, Alistair Francis, 2021/12/20
- [PULL 47/88] target/riscv: rvv-1.0: whole register move instructions, Alistair Francis, 2021/12/20
- [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions, Alistair Francis, 2021/12/20
- [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions,
Alistair Francis <=
- [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, Alistair Francis, 2021/12/20
- [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions, Alistair Francis, 2021/12/20
- [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions, Alistair Francis, 2021/12/20
- [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions, Alistair Francis, 2021/12/20
- [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, Alistair Francis, 2021/12/20
- [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, Alistair Francis, 2021/12/20
- [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, Alistair Francis, 2021/12/20
- [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, Alistair Francis, 2021/12/20
- [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions, Alistair Francis, 2021/12/20