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[PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions
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From: |
Alistair Francis |
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Subject: |
[PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions |
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Date: |
Mon, 20 Dec 2021 14:57:04 +1000 |
From: Vineet Gupta <vineetg@rivosinc.com>
The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9776297c79..6ef3314bce 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -641,10 +641,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* These are experimental so mark with 'x-' */
- DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
- DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
- DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
- DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
+ DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
+ DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
+ DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
--
2.31.1
- [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, (continued)
- [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, Alistair Francis, 2021/12/20
- [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions, Alistair Francis, 2021/12/20
- [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions, Alistair Francis, 2021/12/20
- [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions, Alistair Francis, 2021/12/20
- [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, Alistair Francis, 2021/12/20
- [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, Alistair Francis, 2021/12/20
- [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, Alistair Francis, 2021/12/20
- [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, Alistair Francis, 2021/12/20
- [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions, Alistair Francis, 2021/12/20
- [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions,
Alistair Francis <=
- [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment, Alistair Francis, 2021/12/20
- [PULL 43/88] target/riscv: rvv-1.0: register gather instructions, Alistair Francis, 2021/12/20
- [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions, Alistair Francis, 2021/12/20
- [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions, Alistair Francis, 2021/12/20
- [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction, Alistair Francis, 2021/12/20
- [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, Alistair Francis, 2021/12/20
- [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32, Alistair Francis, 2021/12/20
- [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, Alistair Francis, 2021/12/20
- [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, Alistair Francis, 2021/12/20
- [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions, Alistair Francis, 2021/12/20