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[PULL 17/31] tcg/loongarch64: Implement add/sub ops
From: |
Richard Henderson |
Subject: |
[PULL 17/31] tcg/loongarch64: Implement add/sub ops |
Date: |
Tue, 21 Dec 2021 08:47:23 -0800 |
From: WANG Xuerui <git@xen0n.name>
The neg_i{32,64} ops is fully expressible with sub, so omitted for
simplicity.
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-18-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 38 ++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index 42f8e28741..4b8ce85897 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -18,6 +18,8 @@ C_O0_I1(r)
C_O1_I1(r, r)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
C_O1_I2(r, 0, rZ)
+C_O1_I2(r, rZ, rN)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 2895769e68..c71d25d3fe 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -687,6 +687,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_add_i32:
+ if (c2) {
+ tcg_out_opc_addi_w(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_add_w(s, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_add_i64:
+ if (c2) {
+ tcg_out_opc_addi_d(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_add_d(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_sub_i32:
+ if (c2) {
+ tcg_out_opc_addi_w(s, a0, a1, -a2);
+ } else {
+ tcg_out_opc_sub_w(s, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_sub_i64:
+ if (c2) {
+ tcg_out_opc_addi_d(s, a0, a1, -a2);
+ } else {
+ tcg_out_opc_sub_d(s, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -748,6 +778,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_rotr_i64:
return C_O1_I2(r, r, ri);
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ return C_O1_I2(r, r, rI);
+
case INDEX_op_and_i32:
case INDEX_op_and_i64:
case INDEX_op_nor_i32:
@@ -770,6 +804,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
/* Must deposit into the same register as input */
return C_O1_I2(r, 0, rZ);
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ return C_O1_I2(r, rZ, rN);
+
default:
g_assert_not_reached();
}
--
2.25.1
- [PULL 05/31] tcg/loongarch64: Add register names, allocation order and input/output sets, (continued)
- [PULL 05/31] tcg/loongarch64: Add register names, allocation order and input/output sets, Richard Henderson, 2021/12/21
- [PULL 09/31] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi, Richard Henderson, 2021/12/21
- [PULL 04/31] tcg/loongarch64: Add generated instruction opcodes and encoding helpers, Richard Henderson, 2021/12/21
- [PULL 07/31] tcg/loongarch64: Implement necessary relocation operations, Richard Henderson, 2021/12/21
- [PULL 06/31] tcg/loongarch64: Define the operand constraints, Richard Henderson, 2021/12/21
- [PULL 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops, Richard Henderson, 2021/12/21
- [PULL 13/31] tcg/loongarch64: Implement deposit/extract ops, Richard Henderson, 2021/12/21
- [PULL 12/31] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops, Richard Henderson, 2021/12/21
- [PULL 15/31] tcg/loongarch64: Implement clz/ctz ops, Richard Henderson, 2021/12/21
- [PULL 16/31] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops, Richard Henderson, 2021/12/21
- [PULL 17/31] tcg/loongarch64: Implement add/sub ops,
Richard Henderson <=
- [PULL 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops, Richard Henderson, 2021/12/21
- [PULL 19/31] tcg/loongarch64: Implement br/brcond ops, Richard Henderson, 2021/12/21
- [PULL 11/31] tcg/loongarch64: Implement sign-/zero-extension ops, Richard Henderson, 2021/12/21
- [PULL 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops, Richard Henderson, 2021/12/21
- [PULL 20/31] tcg/loongarch64: Implement setcond ops, Richard Henderson, 2021/12/21
- [PULL 26/31] tcg/loongarch64: Implement tcg_target_init, Richard Henderson, 2021/12/21
- [PULL 08/31] tcg/loongarch64: Implement the memory barrier op, Richard Henderson, 2021/12/21
- [PULL 22/31] tcg/loongarch64: Implement simple load/store ops, Richard Henderson, 2021/12/21
- [PULL 10/31] tcg/loongarch64: Implement goto_ptr, Richard Henderson, 2021/12/21
- [PULL 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue, Richard Henderson, 2021/12/21