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[PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp in
From: |
frank . chang |
Subject: |
[PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns |
Date: |
Wed, 29 Dec 2021 10:33:33 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 41 +++++++++++++++++++------
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index a1e403fe86..0aa8b7918f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
}
}
+static bool require_zve64f(DisasContext *s)
+{
+ /* RVV + Zve64f = RVV. */
+ if (has_ext(s, RVV)) {
+ return true;
+ }
+
+ /* Zve64f doesn't support FP64. (Section 18.2) */
+ return s->ext_zve64f ? s->sew <= MO_32 : true;
+}
+
/* Destination vector register group cannot overlap source mask register. */
static bool require_vm(int vm, int vd)
{
@@ -2204,7 +2215,8 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
- vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
+ vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+ require_zve64f(s);
}
/* OPFVV without GVEC IR */
@@ -2284,7 +2296,8 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
- vext_check_ss(s, a->rd, a->rs2, a->vm);
+ vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+ require_zve64f(s);
}
/* OPFVF without GVEC IR */
@@ -2501,7 +2514,8 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
/* OPFV instructions ignore vs1 check */
- vext_check_ss(s, a->rd, a->rs2, a->vm);
+ vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+ require_zve64f(s);
}
static bool do_opfv(DisasContext *s, arg_rmr *a,
@@ -2566,7 +2580,8 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
- vext_check_mss(s, a->rd, a->rs1, a->rs2);
+ vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+ require_zve64f(s);
}
GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2579,7 +2594,8 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
- vext_check_ms(s, a->rd, a->rs2);
+ vext_check_ms(s, a->rd, a->rs2) &&
+ require_zve64f(s);
}
GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -2600,7 +2616,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
- require_align(a->rd, s->lmul)) {
+ require_align(a->rd, s->lmul) &&
+ require_zve64f(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
TCGv_i64 t1;
@@ -3326,7 +3343,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s
*a)
{
if (require_rvv(s) &&
require_rvf(s) &&
- vext_check_isa_ill(s)) {
+ vext_check_isa_ill(s) &&
+ require_zve64f(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
unsigned int ofs = (8 << s->sew);
@@ -3352,7 +3370,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f
*a)
{
if (require_rvv(s) &&
require_rvf(s) &&
- vext_check_isa_ill(s)) {
+ vext_check_isa_ill(s) &&
+ require_zve64f(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
/* The instructions ignore LMUL and vector register group. */
@@ -3403,13 +3422,15 @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx,
slidedown_check)
static bool fslideup_check(DisasContext *s, arg_rmrr *a)
{
return slideup_check(s, a) &&
- require_rvf(s);
+ require_rvf(s) &&
+ require_zve64f(s);
}
static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
{
return slidedown_check(s, a) &&
- require_rvf(s);
+ require_rvf(s) &&
+ require_zve64f(s);
}
GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
--
2.31.1
- [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, frank . chang, 2021/12/28
- [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, frank . chang, 2021/12/28
- [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, frank . chang, 2021/12/28
- [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, frank . chang, 2021/12/28
- [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2021/12/28
- [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2021/12/28
- [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns,
frank . chang <=
- [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2021/12/28
- [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, frank . chang, 2021/12/28
- [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, frank . chang, 2021/12/28
- [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, frank . chang, 2021/12/28
- [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2021/12/28
- [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, frank . chang, 2021/12/28
- [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, frank . chang, 2021/12/28
- [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, frank . chang, 2021/12/28
- [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, frank . chang, 2021/12/28
- [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, frank . chang, 2021/12/28