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[PATCH v1 2/5] RISC-V: monitor's print register functionality
From: |
Konrad Schwarz |
Subject: |
[PATCH v1 2/5] RISC-V: monitor's print register functionality |
Date: |
Sun, 2 Jan 2022 17:06:09 +0100 |
Enable the print (p) command to display both
general-purpose and Contral and Status (CSR) registers.
General purpose registers can be named using the xN form
or their ABI names (zero, ra, sp, a0, s1, t2).
Signed-off-by: Konrad Schwarz <konrad.schwarz@siemens.com>
---
target/riscv/monitor.c | 69 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 7efb4b62c1..3f74ea9934 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -2,6 +2,7 @@
* QEMU monitor for RISC-V
*
* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (c) 2021 Siemens AG, konrad.schwarz@siemens.com
*
* RISC-V specific monitor commands implementation
*
@@ -234,3 +235,71 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
mem_info_svxx(mon, env);
}
+
+static const MonitorDef monitor_defs[] = {
+# define MONITORDEF_RISCV_GPR(NO, ALIAS)\
+ { "x" #NO #ALIAS, offsetof(CPURISCVState, gpr[NO]) },
+
+ MONITORDEF_RISCV_GPR(0, |zero)
+ MONITORDEF_RISCV_GPR(1, |ra)
+ MONITORDEF_RISCV_GPR(2, |sp)
+ MONITORDEF_RISCV_GPR(3, |gp)
+ MONITORDEF_RISCV_GPR(4, |tp)
+ MONITORDEF_RISCV_GPR(5, |t0)
+ MONITORDEF_RISCV_GPR(6, |t1)
+ MONITORDEF_RISCV_GPR(7, |t2)
+ MONITORDEF_RISCV_GPR(8, |s0|fp)
+ MONITORDEF_RISCV_GPR(9, |s1)
+ MONITORDEF_RISCV_GPR(10, |a0)
+ MONITORDEF_RISCV_GPR(11, |a1)
+ MONITORDEF_RISCV_GPR(12, |a2)
+ MONITORDEF_RISCV_GPR(13, |a3)
+ MONITORDEF_RISCV_GPR(14, |a4)
+ MONITORDEF_RISCV_GPR(15, |a5)
+ MONITORDEF_RISCV_GPR(16, |a6)
+ MONITORDEF_RISCV_GPR(17, |a7)
+ MONITORDEF_RISCV_GPR(18, |s2)
+ MONITORDEF_RISCV_GPR(19, |s3)
+ MONITORDEF_RISCV_GPR(20, |s4)
+ MONITORDEF_RISCV_GPR(21, |s5)
+ MONITORDEF_RISCV_GPR(22, |s6)
+ MONITORDEF_RISCV_GPR(23, |s7)
+ MONITORDEF_RISCV_GPR(24, |s8)
+ MONITORDEF_RISCV_GPR(25, |s9)
+ MONITORDEF_RISCV_GPR(26, |s10)
+ MONITORDEF_RISCV_GPR(27, |s11)
+ MONITORDEF_RISCV_GPR(28, |t3)
+ MONITORDEF_RISCV_GPR(29, |t4)
+ MONITORDEF_RISCV_GPR(30, |t5)
+ MONITORDEF_RISCV_GPR(31, |t6)
+
+ { },
+};
+
+const MonitorDef *target_monitor_defs(void)
+{
+ return monitor_defs;
+}
+
+int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
+{
+
+ target_ulong ret_value;
+ CPURISCVState *const env = &RISCV_CPU (cs)->env;
+ riscv_csr_operations *op;
+ for (op = csr_ops; 1[&csr_ops] > op; ++op) {
+ if (!op->name) {
+ continue;
+ }
+ if (!strcmp(name, op->name)) {
+ if (RISCV_EXCP_NONE != riscv_csrrw_debug(env, op - csr_ops,
+ &ret_value,
+ 0 /* new_value */,
+ 0 /* write_mask */))
+ return -1;
+ *pval = ret_value;
+ return 0;
+ }
+ }
+ return -1;
+}
--
Konrad Schwarz
- [PATCH v1 0/5] Improve RISC-V debugging support., Konrad Schwarz, 2022/01/02
- [PATCH v1 2/5] RISC-V: monitor's print register functionality,
Konrad Schwarz <=
- [PATCH v1 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Konrad Schwarz, 2022/01/02
- [PATCH v1 1/5] RISC-V: larger and more consistent register set for 'info registers', Konrad Schwarz, 2022/01/02
- [PATCH v1 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register, Konrad Schwarz, 2022/01/02
- [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver, Konrad Schwarz, 2022/01/02
- Re: [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver, Ralf Ramsauer, 2022/01/03
- [PATCH v2 0/5] Improve RISC-V debugging support., Konrad Schwarz, 2022/01/04
- [PATCH v2 2/5] RISC-V: monitor's print register functionality, Konrad Schwarz, 2022/01/04
- [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Konrad Schwarz, 2022/01/04
- Re: [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Alistair Francis, 2022/01/04
- RE: [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Schwarz, Konrad, 2022/01/05