Re: [PATCH v2 5/6] target/hppa: Implement prctl_unalign_sigbus

[Laurent Vivier]

Le 27/12/2021 à 16:01, Richard Henderson a écrit :
> Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
> flag to set MO_UNALN for the instructions that the kernel
> handles in the unaligned trap.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   linux-user/hppa/target_prctl.h |  2 +-
>   target/hppa/cpu.h              |  5 ++++-
>   target/hppa/translate.c        | 19 +++++++++++++++----
>   3 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h
> index eb53b31ad5..5629ddbf39 100644
> --- a/linux-user/hppa/target_prctl.h
> +++ b/linux-user/hppa/target_prctl.h
> @@ -1 +1 @@
> -/* No special prctl support required. */
> +#include "../generic/target_prctl_unalign.h"
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 294fd7297f..45fd338b02 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState 
> *env, uint64_t spc,
>       return hppa_form_gva_psw(env->psw, spc, off);
>   }
>   
> -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
> +/*
> + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
>    * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
>    * same value.
>    */
>   #define TB_FLAG_SR_SAME     PSW_I
>   #define TB_FLAG_PRIV_SHIFT  8
> +#define TB_FLAG_UNALIGN     0x400
>   
>   static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
>                                           target_ulong *cs_base,
> @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, 
> target_ulong *pc,
>   #ifdef CONFIG_USER_ONLY
>       *pc = env->iaoq_f & -4;
>       *cs_base = env->iaoq_b & -4;
> +    flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
>   #else
>       /* ??? E, T, H, L, B, P bits need to be here, when implemented.  */
>       flags |= env->psw & (PSW_W | PSW_C | PSW_D);
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index 952027a28e..a2392a1b64 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -274,8 +274,18 @@ typedef struct DisasContext {
>       int mmu_idx;
>       int privilege;
>       bool psw_n_nonzero;
> +
> +#ifdef CONFIG_USER_ONLY
> +    MemOp unalign;
> +#endif
>   } DisasContext;
>   
> +#ifdef CONFIG_USER_ONLY
> +#define UNALIGN(C)  (C)->unalign
> +#else
> +#define UNALIGN(C)  0
> +#endif
> +
>   /* Note that ssm/rsm instructions number PSW_W and PSW_E differently.  */
>   static int expand_sm_imm(DisasContext *ctx, int val)
>   {
> @@ -1475,7 +1485,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, 
> unsigned rb,
>   
>       form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
>                ctx->mmu_idx == MMU_PHYS_IDX);
> -    tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop);
> +    tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
>       if (modify) {
>           save_gpr(ctx, rb, ofs);
>       }
> @@ -1493,7 +1503,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, 
> unsigned rb,
>   
>       form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
>                ctx->mmu_idx == MMU_PHYS_IDX);
> -    tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop);
> +    tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
>       if (modify) {
>           save_gpr(ctx, rb, ofs);
>       }
> @@ -1511,7 +1521,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, 
> unsigned rb,
>   
>       form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
>                ctx->mmu_idx == MMU_PHYS_IDX);
> -    tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop);
> +    tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
>       if (modify) {
>           save_gpr(ctx, rb, ofs);
>       }
> @@ -1529,7 +1539,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, 
> unsigned rb,
>   
>       form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
>                ctx->mmu_idx == MMU_PHYS_IDX);
> -    tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop);
> +    tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
>       if (modify) {
>           save_gpr(ctx, rb, ofs);
>       }
> @@ -4107,6 +4117,7 @@ static void hppa_tr_init_disas_context(DisasContextBase 
> *dcbase, CPUState *cs)
>       ctx->mmu_idx = MMU_USER_IDX;
>       ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX;
>       ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX;
> +    ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
>   #else
>       ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
>       ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);

Applied to my linux-user-for-7.0 branch.

Thanks,
Laurent