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[PATCH v7 04/23] target/riscv: Improve delivery of guest external interr
From: |
Anup Patel |
Subject: |
[PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts |
Date: |
Mon, 17 Jan 2022 18:58:07 +0530 |
From: Anup Patel <anup.patel@wdc.com>
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu_helper.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index aabf0a02f9..01a8baea06 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -325,6 +325,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
}
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+
+ if (enable) {
+ /*
+ * The guest external interrupts from an interrupt controller are
+ * delivered only when the Guest/VM is running (i.e. V=1). This means
+ * any guest external interrupt which is triggered while the Guest/VM
+ * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+ * with sluggish response to serial console input and other I/O events.
+ *
+ * To solve this, we check and inject interrupt after setting V=1.
+ */
+ riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+ }
}
bool riscv_cpu_two_stage_lookup(int mmu_idx)
--
2.25.1
- [PATCH v7 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, (continued)
- [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2022/01/17
- [PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2022/01/17
- [PATCH v7 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2022/01/17
- [PATCH v7 14/23] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2022/01/17
- [PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts,
Anup Patel <=
- [PATCH v7 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2022/01/17
- [PATCH v7 07/23] target/riscv: Add defines for AIA CSRs, Anup Patel, 2022/01/17
- [PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs, Anup Patel, 2022/01/17
- [PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Anup Patel, 2022/01/17
- [PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2022/01/17
- [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation, Anup Patel, 2022/01/17
- [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation, Anup Patel, 2022/01/17
- [PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2022/01/17