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Re: [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type
From: |
Alex Bennée |
Subject: |
Re: [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type |
Date: |
Thu, 27 Jan 2022 12:05:00 +0000 |
User-agent: |
mu4e 1.7.6; emacs 28.0.91 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Ben Widawsky <ben.widawsky@intel.com>
>
> The easiest way to differentiate a CXL bus, and a PCIE bus is using a
> flag. A CXL bus, in hardware, is backward compatible with PCIE, and
> therefore the code tries pretty hard to keep them in sync as much as
> possible.
>
> The other way to implement this would be to try to cast the bus to the
> correct type. This is less code and useful for debugging via simply
> looking at the flags.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
- Re: [PATCH v4 07/42] hw/cxl/device: Add memory device utilities, (continued)
- [PATCH v4 09/42] hw/cxl/device: Timestamp implementation (8.2.9.3), Jonathan Cameron, 2022/01/24
- [PATCH v4 10/42] hw/cxl/device: Add log commands (8.2.9.4) + CEL, Jonathan Cameron, 2022/01/24
- [PATCH v4 11/42] hw/pxb: Use a type for realizing expanders, Jonathan Cameron, 2022/01/24
- [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type, Jonathan Cameron, 2022/01/24
- Re: [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type,
Alex Bennée <=
- [PATCH v4 13/42] hw/pxb: Allow creation of a CXL PXB (host bridge), Jonathan Cameron, 2022/01/24
- [PATCH v4 14/42] tests/acpi: allow DSDT.viot table changes., Jonathan Cameron, 2022/01/24
[PATCH v4 15/42] acpi/pci: Consolidate host bridge setup, Jonathan Cameron, 2022/01/24