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[RFC PATCH v5 25/30] hw/loongarch: Add default bios startup support.
From: |
Xiaojuan Yang |
Subject: |
[RFC PATCH v5 25/30] hw/loongarch: Add default bios startup support. |
Date: |
Thu, 27 Jan 2022 22:44:07 -0500 |
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/Kconfig | 4 ++++
hw/loongarch/fw_cfg.c | 33 ++++++++++++++++++++++++++++++
hw/loongarch/fw_cfg.h | 15 ++++++++++++++
hw/loongarch/loongson3.c | 35 ++++++++++++++++++++++++++++++++
hw/loongarch/meson.build | 1 +
include/hw/loongarch/loongarch.h | 8 ++++++++
6 files changed, 96 insertions(+)
create mode 100644 hw/loongarch/fw_cfg.c
create mode 100644 hw/loongarch/fw_cfg.h
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index 0f759eaa37..06bfb82b1d 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -13,3 +13,7 @@ config LOONGSON3_LS7A
select LOONGARCH_PCH_MSI
select LOONGARCH_EXTIOI
select LS7A_RTC
+ select FW_CFG_LOONGARCH
+
+config FW_CFG_LOONGARCH
+ bool
diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c
new file mode 100644
index 0000000000..4cefffc896
--- /dev/null
+++ b/hw/loongarch/fw_cfg.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU fw_cfg helpers (LoongArch specific)
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/loongarch/fw_cfg.h"
+#include "hw/loongarch/loongarch.h"
+#include "hw/nvram/fw_cfg.h"
+#include "sysemu/sysemu.h"
+
+static void fw_cfg_boot_set(void *opaque, const char *boot_device,
+ Error **errp)
+{
+ fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
+}
+
+FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms)
+{
+ FWCfgState *fw_cfg;
+ int max_cpus = ms->smp.max_cpus;
+ int smp_cpus = ms->smp.cpus;
+
+ fw_cfg = fw_cfg_init_mem_wide(FW_CFG_ADDR + 8, FW_CFG_ADDR, 8, 0, NULL);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
+
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
+ return fw_cfg;
+}
diff --git a/hw/loongarch/fw_cfg.h b/hw/loongarch/fw_cfg.h
new file mode 100644
index 0000000000..7c0de4db4a
--- /dev/null
+++ b/hw/loongarch/fw_cfg.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU fw_cfg helpers (LoongArch specific)
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_FW_CFG_H
+#define HW_LOONGARCH_FW_CFG_H
+
+#include "hw/boards.h"
+#include "hw/nvram/fw_cfg.h"
+
+FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms);
+#endif
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 8155645bd3..ef46a5cfc4 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -17,6 +17,8 @@
#include "sysemu/reset.h"
#include "hw/irq.h"
#include "net/net.h"
+#include "hw/loader.h"
+#include "elf.h"
#include "hw/loongarch/loongarch.h"
#include "hw/intc/loongarch_ipi.h"
#include "hw/intc/loongarch_extioi.h"
@@ -24,9 +26,12 @@
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/pci-host/ls7a.h"
#include "hw/misc/unimp.h"
+#include "hw/loongarch/fw_cfg.h"
#include "target/loongarch/cpu.h"
+#define LOONGSON3_BIOSNAME "loongarch_bios.bin"
+
static void loongarch_cpu_reset(void *opaque)
{
LoongArchCPU *cpu = opaque;
@@ -258,6 +263,8 @@ static void loongarch_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
int i;
+ int bios_size;
+ char *filename;
if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
@@ -289,6 +296,11 @@ static void loongarch_init(MachineState *machine)
}
+ if (ram_size < 1 * GiB) {
+ error_report("ram_size must be greater than 1G.");
+ exit(1);
+ }
+
/* Add memory region */
memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
machine->ram, 0, 256 * MiB);
@@ -307,6 +319,28 @@ static void loongarch_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE,
&lams->isa_io);
+ /* load the BIOS image. */
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
+ machine->firmware ?: LOONGSON3_BIOSNAME);
+ if (filename) {
+ bios_size = load_image_targphys(filename, LA_BIOS_BASE, LA_BIOS_SIZE);
+ lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine);
+ rom_set_fw(lams->fw_cfg);
+ g_free(filename);
+ } else {
+ bios_size = -1;
+ }
+
+ if ((bios_size < 0 || bios_size > LA_BIOS_SIZE) && !qtest_enabled()) {
+ error_report("Could not load LOONGARCH bios '%s'", machine->firmware);
+ exit(1);
+ }
+
+ memory_region_init_ram(&lams->bios, NULL, "loongarch.bios",
+ LA_BIOS_SIZE, &error_fatal);
+ memory_region_set_readonly(&lams->bios, true);
+ memory_region_add_subregion(get_system_memory(), LA_BIOS_BASE,
&lams->bios);
+
/* Initialize the IO interrupt subsystem */
loongarch_irq_init(lams);
}
@@ -322,6 +356,7 @@ static void loongarch_class_init(ObjectClass *oc, void
*data)
mc->default_ram_id = "loongarch.ram";
mc->max_cpus = LOONGARCH_MAX_VCPUS;
mc->is_default = 1;
+ mc->default_machine_opts = "firmware=loongarch_bios.bin";
mc->default_kernel_irqchip_split = false;
mc->block_default_type = IF_VIRTIO;
mc->default_boot_order = "c";
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
index 1db3529cbc..fed69dfb62 100644
--- a/hw/loongarch/meson.build
+++ b/hw/loongarch/meson.build
@@ -1,4 +1,5 @@
loongarch_ss = ss.source_set()
loongarch_ss.add(when: 'CONFIG_LOONGSON3_LS7A', if_true: files('loongson3.c'))
+loongarch_ss.add(when: 'CONFIG_FW_CFG_LOONGARCH', if_true: files('fw_cfg.c'))
hw_arch += {'loongarch': loongarch_ss}
diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
index 4a889267af..9df755513b 100644
--- a/include/hw/loongarch/loongarch.h
+++ b/include/hw/loongarch/loongarch.h
@@ -37,6 +37,10 @@
#define LOONGARCH_ISA_IO_BASE 0x18000000UL
#define LOONGARCH_ISA_IO_SIZE 0x0004000
+#define FW_CFG_ADDR 0x1e020000
+#define LA_BIOS_BASE 0x1c000000
+#define LA_BIOS_SIZE (4 * 1024 * 1024)
+
typedef struct LoongArchMachineState {
/*< private >*/
MachineState parent_obj;
@@ -44,6 +48,10 @@ typedef struct LoongArchMachineState {
MemoryRegion lowmem;
MemoryRegion highmem;
MemoryRegion isa_io;
+ MemoryRegion bios;
+
+ /* State for other subsystems/APIs: */
+ FWCfgState *fw_cfg;
} LoongArchMachineState;
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson3-ls7a")
--
2.27.0
- [RFC PATCH v5 16/30] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC), (continued)
- [RFC PATCH v5 16/30] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC), Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 22/30] Enable common virtio pci support for LoongArch, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 10/30] target/loongarch: Add other core instructions support, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 14/30] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3 Platform, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 27/30] hw/loongarch: Add LoongArch smbios support, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 19/30] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI), Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 15/30] hw/loongarch: Add support loongson3-ls7a machine type., Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 18/30] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC), Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 26/30] hw/loongarch: Add -kernel and -initrd options support, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 28/30] hw/loongarch: Add LoongArch acpi support, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 25/30] hw/loongarch: Add default bios startup support.,
Xiaojuan Yang <=
- [RFC PATCH v5 24/30] hw/loongarch: Add LoongArch ls7a rtc device support, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 21/30] hw/loongarch: Add irq hierarchy for the system, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 30/30] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system, Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 29/30] hw/loongarch: Add fdt support., Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 23/30] hw/loongarch: Add some devices support for 3A5000., Xiaojuan Yang, 2022/01/27
- [RFC PATCH v5 20/30] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC), Xiaojuan Yang, 2022/01/27