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Re: [PATCH v5 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCon
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps |
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Date: |
Tue, 1 Feb 2022 13:10:57 +1000 |
On Mon, Jan 31, 2022 at 9:24 PM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> The XVentanaCondOps extension is supported by VRULL on behalf of the
> Ventana Micro. Add myself as a point-of-contact.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - add a MAINTAINERS entry for XVentanaCondOps
>
> MAINTAINERS | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b43344fa98..2e0b2ae947 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -286,6 +286,13 @@ F: include/hw/riscv/
> F: linux-user/host/riscv32/
> F: linux-user/host/riscv64/
>
> +RISC-V XVentanaCondOps extension
> +M: Philipp Tomsich <philipp.tomsich@vrull.eu>
> +L: qemu-riscv@nongnu.org
> +S: Supported
> +F: target/riscv/XVentanaCondOps.decode
> +F: target/riscv/insn_trans/trans_xventanacondops.c.inc
> +
> RENESAS RX CPUs
> R: Yoshinori Sato <ysato@users.sourceforge.jp>
> S: Orphan
> --
> 2.33.1
>
>
- [PATCH v5 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes, Philipp Tomsich, 2022/01/31
- [PATCH v5 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Philipp Tomsich, 2022/01/31
- [PATCH v5 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Philipp Tomsich, 2022/01/31
- [PATCH v5 4/7] target/riscv: access cfg structure through DisasContext, Philipp Tomsich, 2022/01/31
- [PATCH v5 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Philipp Tomsich, 2022/01/31
- Re: [PATCH v5 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps,
Alistair Francis <=
- [PATCH v5 5/7] target/riscv: iterate over a table of decoders, Philipp Tomsich, 2022/01/31
- [PATCH v5 3/7] target/riscv: access configuration through cfg_ptr in DisasContext, Philipp Tomsich, 2022/01/31
- [PATCH v5 6/7] target/riscv: Add XVentanaCondOps custom extension, Philipp Tomsich, 2022/01/31