Re: [PULL 53/61] target/riscv: Split out the vill from vtype

[LIU Zhiwei]

On 2022/2/1 10:12, Alistair Francis wrote:
> On Sat, Jan 29, 2022 at 2:10 AM Peter Maydell <peter.maydell@linaro.org> wrote:
> > On Fri, 21 Jan 2022 at 09:42, Alistair Francis
> > <alistair.francis@opensource.wdc.com> wrote:
> > > From: LIU Zhiwei <zhiwei_liu@c-sky.com>
> > >
> > > We need not specially process vtype when XLEN changes.
> > >
> > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > > Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Odd thing I noticed looking at this code: as far as I can see we
> > may set env->vill to 1 in the vsetvl helper, but there is nowhere
> > that we set it to 0, so once it transitions to 1 it's stuck there
> > until the system is reset. Is this really right?
> This is really confusing. It implies that you can't set vill from
> software, but that just seems to be confusing wording.
>
> Reading 
> https://lists.riscv.org/g/tech-vector-ext/topic/reliably_set_vtype_vill/86745728
> it seems that this is a QEMU bug and the guest should be able to set
> the bit as part of vsetvl
>
> @LIU Zhiwei are you able to fix this up?

Thanks for pointing it out. I have sent a patch to fix this up.

Thanks,
Zhiwei

> Alistair