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Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH 11/15] target: Use ArchCPU as interface to target CPU |
Date: |
Wed, 9 Feb 2022 23:33:43 +0100 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 |
On 9/2/22 22:54, Philippe Mathieu-Daudé wrote:
ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/qemu/typedefs.h | 1 +
target/alpha/cpu-qom.h | 4 +++-
target/alpha/cpu.h | 4 +---
target/arm/cpu-qom.h | 4 +++-
target/arm/cpu.h | 2 --
target/avr/cpu-qom.h | 4 +++-
target/avr/cpu.h | 6 ++----
target/cris/cpu-qom.h | 4 +++-
target/cris/cpu.h | 4 +---
target/hexagon/cpu.h | 2 +-
target/hppa/cpu-qom.h | 4 +++-
target/hppa/cpu.h | 4 +---
target/i386/cpu-qom.h | 4 +++-
target/i386/cpu.h | 4 +---
target/m68k/cpu-qom.h | 4 +++-
target/m68k/cpu.h | 4 +---
target/microblaze/cpu-qom.h | 4 +++-
target/microblaze/cpu.h | 6 +++---
target/mips/cpu-qom.h | 4 +++-
target/mips/cpu.h | 4 +---
target/nios2/cpu.h | 4 ++--
target/openrisc/cpu.h | 11 ++++-------
target/ppc/cpu-qom.h | 4 +++-
target/ppc/cpu.h | 4 +---
target/riscv/cpu.h | 5 ++---
target/rx/cpu-qom.h | 4 +++-
target/rx/cpu.h | 4 +---
target/s390x/cpu-qom.h | 4 +++-
target/s390x/cpu.h | 4 +---
target/sh4/cpu-qom.h | 4 +++-
target/sh4/cpu.h | 4 +---
target/sparc/cpu-qom.h | 4 +++-
target/sparc/cpu.h | 4 +---
target/tricore/cpu-qom.h | 4 +++-
target/tricore/cpu.h | 4 +---
target/xtensa/cpu-qom.h | 4 +++-
target/xtensa/cpu.h | 4 +---
37 files changed, 76 insertions(+), 77 deletions(-)
...
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index a22bd506d0..b0a0724e8c 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -27,7 +27,9 @@ struct arm_boot_info;
#define TYPE_ARM_CPU "arm-cpu"
-OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
+typedef struct ArchCPU ARMCPU;
+
+OBJECT_DECLARE_TYPE(ArchCPU, ARMCPUClass,
ARM_CPU)
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a95a070647..a137c564c4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState
*env)
}
}
-typedef ARMCPU ArchCPU;
-
#include "exec/cpu-all.h"
/*
...
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 79144ddc24..5981be47d9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -285,7 +285,7 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
-OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
+OBJECT_DECLARE_TYPE(ArchCPU, RISCVCPUClass,
RISCV_CPU)
/**
@@ -309,7 +309,7 @@ struct RISCVCPUClass {
*
* A RISCV CPU.
*/
-struct RISCVCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@@ -430,7 +430,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
-typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
Sorry I messed while rebasing, this hunk is missing:
-- >8 --
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a137c564c4..a4bbca1812 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -774,7 +774,7 @@ typedef struct ARMISARegisters ARMISARegisters;
*
* An ARM CPU core.
*/
-struct ARMCPU {
+struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 05def159b1..6a243cfc06 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -171,7 +171,7 @@ struct CPUArchState {
*
* A Nios2 CPU.
*/
-struct ArchCPU {
+typedef struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@@ -188,7 +188,7 @@ struct ArchCPU {
uint32_t reset_addr;
uint32_t exception_addr;
uint32_t fast_tlb_miss_addr;
-};
+} Nios2CPU;
void nios2_tcg_init(void);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5981be47d9..d8fefcbc4e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -309,7 +309,7 @@ struct RISCVCPUClass {
*
* A RISCV CPU.
*/
-struct ArchCPU {
+typedef struct ArchCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@@ -357,7 +357,7 @@ struct ArchCPU {
bool epmp;
uint64_t resetvec;
} cfg;
-};
+} RISCVCPU;
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
---
- Re: [PATCH 03/15] hw/tricore: Remove unused and incorrect header, (continued)
- [PATCH 04/15] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition, Philippe Mathieu-Daudé, 2022/02/09
- [PATCH 05/15] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers, Philippe Mathieu-Daudé, 2022/02/09
- [PATCH 06/15] target/i386/cpu: Ensure accelerators set CPU addressble physical bits, Philippe Mathieu-Daudé, 2022/02/09
- [PATCH 07/15] target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header, Philippe Mathieu-Daudé, 2022/02/09
- [PATCH 08/15] target: Include missing 'cpu.h', Philippe Mathieu-Daudé, 2022/02/09
- [PATCH 09/15] target: Use forward declared type instead of structure type, Philippe Mathieu-Daudé, 2022/02/09
- [PATCH 10/15] target: Use CPUArchState as interface to target-specific CPU state, Philippe Mathieu-Daudé, 2022/02/09
- [PATCH 11/15] target: Use ArchCPU as interface to target CPU, Philippe Mathieu-Daudé, 2022/02/09
[RFC PATCH 12/15] hw/m68k: Restrict M68kCPU type to target/ code, Philippe Mathieu-Daudé, 2022/02/09
[RFC PATCH 13/15] hw/mips: Restrict MIPSCPU type to target/ code, Philippe Mathieu-Daudé, 2022/02/09