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[PULL 02/40] Allow setting up to 8 bytes with the generic loader
From: |
Alistair Francis |
Subject: |
[PULL 02/40] Allow setting up to 8 bytes with the generic loader |
Date: |
Sat, 12 Feb 2022 09:59:53 +1000 |
From: Petr Tesarik <ptesarik@suse.com>
The documentation for the generic loader says that "the maximum size of
the data is 8 bytes". However, attempts to set data-len=8 trigger the
following assertion failure:
../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_len <
sizeof(s->data)' failed.
The type of s->data is uint64_t (i.e. 8 bytes long), so I believe this
assert should use <= instead of <.
Fixes: e481a1f63c93 ("generic-loader: Add a generic loader")
Signed-off-by: Petr Tesarik <ptesarik@suse.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120092715.7805-1-ptesarik@suse.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/core/generic-loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index 9a24ffb880..504ed7ca72 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -56,7 +56,7 @@ static void generic_loader_reset(void *opaque)
}
if (s->data_len) {
- assert(s->data_len < sizeof(s->data));
+ assert(s->data_len <= sizeof(s->data));
dma_memory_write(s->cpu->as, s->addr, &s->data, s->data_len,
MEMTXATTRS_UNSPECIFIED);
}
--
2.34.1
- [PULL 00/40] riscv-to-apply queue, Alistair Francis, 2022/02/11
- [PULL 01/40] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/11
- [PULL 02/40] Allow setting up to 8 bytes with the generic loader,
Alistair Francis <=
- [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/11
- [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Alistair Francis, 2022/02/11
- [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Alistair Francis, 2022/02/11
- [PULL 07/40] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/11
- [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/11
- [PULL 08/40] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/11
- [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/11
- [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/11
- [PULL 11/40] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/11
- [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/11