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[PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-
From: |
Alistair Francis |
Subject: |
[PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr |
Date: |
Sat, 12 Feb 2022 09:59:56 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-3-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0bbe80875..49e40735ce 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,6 +76,7 @@ typedef struct DisasContext {
int frm;
RISCVMXL ol;
bool virt_enabled;
+ const RISCVCPUConfig *cfg_ptr;
bool ext_ifencei;
bool ext_zfh;
bool ext_zfhmin;
@@ -908,6 +909,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
#endif
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
+ ctx->cfg_ptr = &(cpu->cfg);
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->ext_zfh = cpu->cfg.ext_zfh;
ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
--
2.34.1
- [PULL 00/40] riscv-to-apply queue, Alistair Francis, 2022/02/11
- [PULL 01/40] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/11
- [PULL 02/40] Allow setting up to 8 bytes with the generic loader, Alistair Francis, 2022/02/11
- [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/11
- [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Alistair Francis, 2022/02/11
- [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr,
Alistair Francis <=
- [PULL 07/40] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/11
- [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/11
- [PULL 08/40] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/11
- [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/11
- [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/11
- [PULL 11/40] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/11
- [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/11
- [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/11
- [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/11
- [PULL 15/40] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2022/02/11