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[PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
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From: |
Alistair Francis |
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Subject: |
[PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps |
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Date: |
Sat, 12 Feb 2022 10:00:01 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-8-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9814580975..c3f6e70a15 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -286,6 +286,13 @@ F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
+RISC-V XVentanaCondOps extension
+M: Philipp Tomsich <philipp.tomsich@vrull.eu>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/XVentanaCondOps.decode
+F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
S: Orphan
--
2.34.1
- [PULL 00/40] riscv-to-apply queue, Alistair Francis, 2022/02/11
- [PULL 01/40] include: hw: remove ibex_plic.h, Alistair Francis, 2022/02/11
- [PULL 02/40] Allow setting up to 8 bytes with the generic loader, Alistair Francis, 2022/02/11
- [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/11
- [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Alistair Francis, 2022/02/11
- [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Alistair Francis, 2022/02/11
- [PULL 07/40] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/11
- [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/11
- [PULL 08/40] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/11
- [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/11
- [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps,
Alistair Francis <=
- [PULL 11/40] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/11
- [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/11
- [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/11
- [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/11
- [PULL 15/40] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2022/02/11
- [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation, Alistair Francis, 2022/02/11
- [PULL 17/40] target/riscv: Add AIA cpu feature, Alistair Francis, 2022/02/11
- [PULL 18/40] target/riscv: Add defines for AIA CSRs, Alistair Francis, 2022/02/11
- [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 2022/02/11
- [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 2022/02/11