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[PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs
From: |
Alistair Francis |
Subject: |
[PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs |
Date: |
Sat, 12 Feb 2022 10:00:25 +1000 |
From: Anup Patel <anup.patel@wdc.com>
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-24-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 2 +-
hw/riscv/virt.c | 10 ++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d248d0dfa0..78b058ec86 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
#include "hw/block/flash.h"
#include "qom/object.h"
-#define VIRT_CPUS_MAX_BITS 3
+#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
#define VIRT_SOCKETS_MAX_BITS 2
#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c02710f711..7d5f1e58c9 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -45,6 +45,16 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
#if VIRT_IMSIC_GROUP_MAX_SIZE < \
IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
--
2.34.1
- [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs, (continued)
- [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/11
- [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/11
- [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/11
- [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/11
- [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/11
- [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/11
- [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/02/11
- [PULL 33/40] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/02/11
- [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs,
Alistair Francis <=
- [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/11
- [PULL 37/40] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/11
- [PULL 40/40] docs/system: riscv: Update description of CPU, Alistair Francis, 2022/02/11
- [PULL 39/40] target/riscv: add support for svpbmt extension, Alistair Francis, 2022/02/11
- [PULL 38/40] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/11
- [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/11
- Re: [PULL 00/40] riscv-to-apply queue, Peter Maydell, 2022/02/15