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[PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PT
From: |
Alistair Francis |
Subject: |
[PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE |
Date: |
Sat, 12 Feb 2022 10:00:27 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7df4569526..25ebc76725 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -937,6 +937,9 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.34.1
- [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART, (continued)
- [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/11
- [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/11
- [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/11
- [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/11
- [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/11
- [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/02/11
- [PULL 33/40] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/02/11
- [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs, Alistair Francis, 2022/02/11
- [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE,
Alistair Francis <=
- [PULL 37/40] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/11
- [PULL 40/40] docs/system: riscv: Update description of CPU, Alistair Francis, 2022/02/11
- [PULL 39/40] target/riscv: add support for svpbmt extension, Alistair Francis, 2022/02/11
- [PULL 38/40] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/11
- [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/11
- Re: [PULL 00/40] riscv-to-apply queue, Peter Maydell, 2022/02/15