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Re: [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to
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From: |
David Gibson |
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Subject: |
Re: [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header |
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Date: |
Wed, 16 Feb 2022 14:04:26 +1100 |
On Tue, Feb 15, 2022 at 06:41:47PM -0300, Fabiano Rosas wrote:
> These will need to be accessed from other files once we move the CPUs
> code to separate files.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/cpu.h | 57 +++++++++++++++++++++++++++++++++++++++++++
> target/ppc/cpu_init.c | 55 -----------------------------------------
> 2 files changed, 57 insertions(+), 55 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 6a06a7f533..ba0739c43b 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2733,4 +2733,61 @@ void dump_mmu(CPUPPCState *env);
> void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
> void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
> uint32_t ppc_get_vscr(CPUPPCState *env);
> +
> +/*****************************************************************************/
> +/* Power management enable checks
> */
> +static inline int check_pow_none(CPUPPCState *env)
> +{
> + return 0;
> +}
> +
> +static inline int check_pow_nocheck(CPUPPCState *env)
> +{
> + return 1;
> +}
> +
> +static inline int check_pow_hid0(CPUPPCState *env)
I'm a little nervous about moving this to a more exposed location. By
definition the HID register is implementation dependent, and we can
see immediately below that not all things use the same interpretation
of it in practice. So at the very least it seems like it has a bad
name to be exposed more widely. It also seems like it might better
belong next to the code for the cpus that actually use this version.
> +{
> + if (env->spr[SPR_HID0] & 0x00E00000) {
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +static inline int check_pow_hid0_74xx(CPUPPCState *env)
Similar remarks here.
> +{
> + if (env->spr[SPR_HID0] & 0x00600000) {
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +/*****************************************************************************/
> +/* PowerPC implementations definitions
> */
> +
> +#define POWERPC_FAMILY(_name) \
> + static void \
> + glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
> + \
> + static const TypeInfo \
> + glue(glue(ppc_, _name), _cpu_family_type_info) = { \
> + .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
> + .parent = TYPE_POWERPC_CPU, \
> + .abstract = true, \
> + .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
> + }; \
> + \
> + static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
> + { \
> + type_register_static( \
> + &glue(glue(ppc_, _name), _cpu_family_type_info)); \
> + } \
> + \
> + type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
> + \
> + static void glue(glue(ppc_, _name), _cpu_family_class_init)
> +
> +
> #endif /* PPC_CPU_H */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 3327ea15fd..34306e2360 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2484,61 +2484,6 @@ static void init_excp_POWER10(CPUPPCState *env)
>
> #endif
>
> -/*****************************************************************************/
> -/* Power management enable checks
> */
> -static int check_pow_none(CPUPPCState *env)
> -{
> - return 0;
> -}
> -
> -static int check_pow_nocheck(CPUPPCState *env)
> -{
> - return 1;
> -}
> -
> -static int check_pow_hid0(CPUPPCState *env)
> -{
> - if (env->spr[SPR_HID0] & 0x00E00000) {
> - return 1;
> - }
> -
> - return 0;
> -}
> -
> -static int check_pow_hid0_74xx(CPUPPCState *env)
> -{
> - if (env->spr[SPR_HID0] & 0x00600000) {
> - return 1;
> - }
> -
> - return 0;
> -}
> -
> -/*****************************************************************************/
> -/* PowerPC implementations definitions
> */
> -
> -#define POWERPC_FAMILY(_name) \
> - static void \
> - glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
> - \
> - static const TypeInfo \
> - glue(glue(ppc_, _name), _cpu_family_type_info) = { \
> - .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
> - .parent = TYPE_POWERPC_CPU, \
> - .abstract = true, \
> - .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
> - }; \
> - \
> - static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
> - { \
> - type_register_static( \
> - &glue(glue(ppc_, _name), _cpu_family_type_info)); \
> - } \
> - \
> - type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
> - \
> - static void glue(glue(ppc_, _name), _cpu_family_class_init)
> -
> static void init_proc_405(CPUPPCState *env)
> {
> register_40x_sprs(env);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH 15/27] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function, (continued)
- [PATCH 15/27] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function, Fabiano Rosas, 2022/02/15
- [PATCH 20/27] target/ppc: cpu_init: Reuse init_proc_745 for the 755, Fabiano Rosas, 2022/02/15
- [PATCH 25/27] target/ppc: cpu_init: Move SPR registration macros to a header, Fabiano Rosas, 2022/02/15
- [PATCH 27/27] target/ppc: Move common SPR functions out of cpu_init, Fabiano Rosas, 2022/02/15
- [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header, Fabiano Rosas, 2022/02/15
- Re: [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header,
David Gibson <=
- Re: [PATCH 00/27] target/ppc: SPR registration cleanups, David Gibson, 2022/02/15