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[PULL v2 15/35] target/riscv: Improve delivery of guest external interru
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From: |
Alistair Francis |
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Subject: |
[PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts |
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Date: |
Wed, 16 Feb 2022 16:28:52 +1000 |
From: Anup Patel <anup.patel@wdc.com>
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-5-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 698389ba1b..e45ca08ea9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -326,6 +326,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
}
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+
+ if (enable) {
+ /*
+ * The guest external interrupts from an interrupt controller are
+ * delivered only when the Guest/VM is running (i.e. V=1). This means
+ * any guest external interrupt which is triggered while the Guest/VM
+ * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+ * with sluggish response to serial console input and other I/O events.
+ *
+ * To solve this, we check and inject interrupt after setting V=1.
+ */
+ riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+ }
}
bool riscv_cpu_two_stage_lookup(int mmu_idx)
--
2.34.1
- [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128, (continued)
- [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128, Alistair Francis, 2022/02/16
- [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext, Alistair Francis, 2022/02/16
- [PULL v2 07/35] target/riscv: access cfg structure through DisasContext, Alistair Francis, 2022/02/16
- [PULL v2 08/35] target/riscv: iterate over a table of decoders, Alistair Francis, 2022/02/16
- [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension, Alistair Francis, 2022/02/16
- [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Alistair Francis, 2022/02/16
- [PULL v2 11/35] target/riscv: Fix vill field write in vtype, Alistair Francis, 2022/02/16
- [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Alistair Francis, 2022/02/16
- [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/16
- [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/16
- [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts,
Alistair Francis <=
- [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation, Alistair Francis, 2022/02/16
- [PULL v2 17/35] target/riscv: Add AIA cpu feature, Alistair Francis, 2022/02/16
- [PULL v2 18/35] target/riscv: Add defines for AIA CSRs, Alistair Francis, 2022/02/16
- [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 2022/02/16
- [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities, Alistair Francis, 2022/02/16
- [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 2022/02/16
- [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs, Alistair Francis, 2022/02/16
- [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/16
- [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/16
- [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/16