[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 34/35] target/riscv: add support for svpbmt extension
From: |
Alistair Francis |
Subject: |
[PULL v2 34/35] target/riscv: add support for svpbmt extension |
Date: |
Wed, 16 Feb 2022 16:29:11 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU,
since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 2 ++
target/riscv/cpu.c | 1 +
target/riscv/cpu_helper.c | 4 +++-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 37ed4da72c..0fe01d7da5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -561,7 +561,9 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
+#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e5676b40d1..b0a40b83e7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -776,6 +776,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 437c9488a6..746335bfd6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -937,9 +937,11 @@ restart:
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
+ } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
--
2.34.1
- [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs, (continued)
- [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/16
- [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/16
- [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/16
- [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/16
- [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available, Alistair Francis, 2022/02/16
- [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/16
- [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/16
- [PULL v2 32/35] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/16
- [PULL v2 35/35] docs/system: riscv: Update description of CPU, Alistair Francis, 2022/02/16
- [PULL v2 33/35] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/16
- [PULL v2 34/35] target/riscv: add support for svpbmt extension,
Alistair Francis <=
- Re: [PULL v2 00/35] riscv-to-apply queue, Peter Maydell, 2022/02/16