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[PATCH v4 15/47] target/ppc: implement vclrlb
From: |
matheus . ferst |
Subject: |
[PATCH v4 15/47] target/ppc: implement vclrlb |
Date: |
Tue, 22 Feb 2022 11:36:13 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- Branchless implementation (rth)
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/vmx-impl.c.inc | 40 +++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d844d86829..31cdbba86b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -529,6 +529,8 @@ VSTRIBR 000100 ..... 00001 ..... . 0000001101
@VX_tb_rc
VSTRIHL 000100 ..... 00010 ..... . 0000001101 @VX_tb_rc
VSTRIHR 000100 ..... 00011 ..... . 0000001101 @VX_tb_rc
+VCLRLB 000100 ..... ..... ..... 00110001101 @VX
+
# VSX Load/Store Instructions
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 1a69931d36..8f12d78071 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1940,6 +1940,46 @@ TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
+static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 rb, mh, ml, tmp,
+ ones = tcg_constant_i64(-1),
+ zero = tcg_constant_i64(0);
+
+ rb = tcg_temp_new_i64();
+ mh = tcg_temp_new_i64();
+ ml = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(rb, cpu_gpr[a->vrb]);
+ tcg_gen_andi_i64(tmp, rb, 7);
+ tcg_gen_shli_i64(tmp, tmp, 3);
+ tcg_gen_shl_i64(tmp, tcg_constant_i64(-1), tmp);
+ tcg_gen_not_i64(tmp, tmp);
+
+ tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
+ tmp, ones);
+ tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
+ zero, tmp);
+ tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
+ mh, ones);
+
+ get_avr64(tmp, a->vra, true);
+ tcg_gen_and_i64(tmp, tmp, mh);
+ set_avr64(a->vrt, tmp, true);
+
+ get_avr64(tmp, a->vra, false);
+ tcg_gen_and_i64(tmp, tmp, ml);
+ set_avr64(a->vrt, tmp, false);
+
+ tcg_temp_free_i64(rb);
+ tcg_temp_free_i64(mh);
+ tcg_temp_free_i64(ml);
+ tcg_temp_free_i64(tmp);
+
+ return true;
+}
+
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
--
2.25.1
- Re: [PATCH v4 10/47] target/ppc: Move Vector Compare Not Equal or Zero to decodetree, (continued)
- [PATCH v4 09/47] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 12/47] target/ppc: Implement Vector Compare Greater Than Quadword, matheus . ferst, 2022/02/22
- [PATCH v4 11/47] target/ppc: Implement Vector Compare Equal Quadword, matheus . ferst, 2022/02/22
- [PATCH v4 14/47] target/ppc: implement vstri[bh][lr], matheus . ferst, 2022/02/22
- [PATCH v4 13/47] target/ppc: Implement Vector Compare Quadword, matheus . ferst, 2022/02/22
- [PATCH v4 15/47] target/ppc: implement vclrlb,
matheus . ferst <=
- [PATCH v4 16/47] target/ppc: implement vclrrb, matheus . ferst, 2022/02/22
- [PATCH v4 17/47] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/02/22
- [PATCH v4 20/47] target/ppc: implement vslq, matheus . ferst, 2022/02/22
- [PATCH v4 18/47] target/ppc: implement vgnb, matheus . ferst, 2022/02/22